With a new breed of analog/mixed-signal foundries arriving on the scene, fabless and fab-lite companies can create a huge variety of high-yielding designs. As a result, these fabless and fab-lite companies are able to successfully compete with the IDMs in the analog/mixed-signal market. These companies offer something different than traditional CMOS foundries with analog libraries, and it's useful to understand the difference.
Pure-play CMOS foundries have much to offer. Increasing chip density makes it possible to transfer more analog functions into the digital domain. Analog signals are digitized as soon as possible, processed by a digital platform before the data is reconverted to analog output values at the very end of the process.
But that's an oversimplification. There's a need for mixed-signal ICs that encompass digital, analog, high-voltage (HV), radio-frequency (RF), and nonvolatile-memory (NVM) technologies—in many cases, all on the same piece of silicon. Convergence of these different technology platforms can pose serious challenges (Fig. 1).
One such challenge is environmental. Often, analog/mixed-signal devices are required to work in a harsh, unfriendly environment, where they must cope with high temperature differences, high voltages, switching noise, or interference from neighboring elements (Table 1). Analog circuits also are much more sensitive than digital circuits, leaving performance particularly vulnerable.
Mixing technologies creates other challenges. Although the digital world essentially relies on NMOS and PMOS transistors, analog/mixed-signal designs incorporate both CMOS and bipolar junction transistors (BJTs). Another key difference is the presence of a large variety of passive elements, e.g. capacitors, resistors, inductors, varactors, and diodes, which have a major impact on the design's performance. As a result, the ability to accurately construct and model such passives represents a key enabler for new circuits and products (Table 2).
From a process technology perspective, combining a variety of active and passive elements is difficult due to conflicting optimization strategies. Many analog features require their own specific architecture unique modifications of the baseline manufacturing process flow.
More often than not, the necessary additional process steps tend to perturb existing ones due to their different requirements with respect to thermal budget or process sequence. While adhering as closely as possible to the cost-effective bulk CMOS baseline process flow, the challenge is to introduce high-performance HV transistors, passive elements, and NVM blocks without compromising the existing process steps or the cost structure in the foundry environment (Table 3).
Process Technology Analog foundries deal with these challenges with their own approaches to a modular solution. To understand how these work, it's useful to understand how mixed-signal process technologies differ from plain-vanilla CMOS. The architecture of an analog/mixed-signal process is defined by four major issues:
- the passive device architecture
- the active device architecture, driven by the breakdown voltage and on-resistance (RON) trade-off
- the geometry, determined by the amount of logic and memory to implement
- the choice of isolation technique, which is motivated by the requirement to isolate different voltage domains of building blocks and/or chip areas.
High-voltage capability is a special flavor of mixed-signal designs. Apart from the native inner voltage for data processing, which depends on the baseline CMOS technology node—1.8 V for 0.18 µm, 3.3 V for 0.35 µm, or 5 V for processes of 0.6 µm and above—mixed-signal devices may have to cope with higher input or output voltages. Typically, 5 V is needed for analog applications, and voltages above 5 V up to 120 V are required for many applications, such as those in the automotive or industrial domain. As major elements of mixed-signal circuits, HV transistors occupy between 30% and 50% of the overall chip area.
Implementing HV transistors requires fundamental technology choices that affect the cost/performance tradeoff of the design. Available options include lateral or vertical architectures, with junction, trench, or buried layer isolation, using silicon-on-insulator (SOI) technology or a bulk CMOS substrate. High-performance HV devices with optimized, low on-resistance (RON) can be realized in any of these device architectures. Due to the higher complexity of the architectures, the cost/performance tradeoff for vertical devices, buried layer technologies, or deep trench isolation SOI technologies is often skewed toward performance (Table 4 and Fig. 2).
The HV technology choice also depends on the required voltages. For HV transistors operating above approximately 40 V, SOI technologies seem to provide the most promising approach. In contrast, bulk CMOS technology offers the best cost—performance trade-off available today for high-performance transistors below 40 V (Fig. 3).
Another important aspect of HV transistors is scalability—or rather, the current lack of it. In the traditional approach, the most important parameter defining the performance and surface area of a HV transistor, RON, is optimized for a given set of discrete operating voltages. Real life is more diverse, though. It provides a continuum of operating voltages that designers cope with by simply adjusting the lateral geometry of their devices, without having to change the well structure. Such an approach provides an ideal foundry process for the design of HV transistors.
Analog/mixed signal foundries, therefore, put considerable effort into the development of such approaches to realize scalable devices with optimized RON for a wide range of operating voltages. As of today, various ideas exist, but no technology has emerged that reaches this goal reliably or cost-effectively.
Gate-oxide requirements One defining element of HV driver design topology is gate oxide (GOX) thickness, which determines maximum gate voltages. The need to accommodate different voltage domains leads to two competing requirements regarding GOX thickness. To keep the process architecture as simple as possible, HV devices should be developed using the thinnest- possible gate oxide. Adding other HV devices then becomes feasible without the need for more GOX, keeping the process architecture simple. On the other hand, a thin gate oxide requires very fast and reliable gate-protection circuitry, increasing the complexity of the IC design process.Currently known foundry process architectures use two or three GOX thicknesses: at least 6 nm for 3.3-V gate voltages, and 10 nm or thicker for 5-V gate voltages. Even higher gate voltages call for a GOX thickness between 40 and 100 nm, depending on the application. Very thick gate oxides are typical for applications with multiple HV drivers, such as LCD drivers, in which the high GOX thickness simplifies output driver design. The 20-V gate voltages characteristic of robust industrial and automotive applications mainly use 40-nm gate oxides.
A second polysilicon (poly) layer, NVM cells, and thick power metal or power copper options for analog/mixed-signal elements are also required to create high-current routing layers. Extra doping steps are necessary to adjust the resistance values.
Nonvolatile memory options NVM blocks, such as one-time-programmable (OTP) and multiple-time-programmable (MTP) memories, can be implemented in the process architecture without any extra mask layers. On the other hand, embedded Flash (eFlash) and EEPROM cells need a minimum number of additional masks (fewer than 10).Depending on the application, specifications for NVM cells can be very demanding. Automotive specifications, for instance, stipulate junction temperatures ranging from -40°C to 150°C, with a minimum data-retention time of 10 years at 85°C and an endurance of 100,000 cycles with fast write and read times. Highly reliable NVM-cell architectures, in conjunction with error checking and correction techniques like ECC, must consider these requirements. Here, too, designers need to find the proper balance between cost and performance.
Isolation techniques To minimize or eliminate crosstalk and parasitic effects, different areas of the IC must be insulated from each other. The two most widely-used techniques are dielectric isolation and junction isolation. Two possibilities exist for junction isolation. One, the triple-well approach (which makes use of specific well structures) is cost-effective and covers operating voltages up to 60 V (Fig. 5). The other junction isolation approach is based on sinkers and buried layers (Fig. 5, again). This latter technique is typical for bipolar CMOS DMOS (BCD) process architectures, and allows operating voltages up to 200 V.
Dielectric isolation is realized using up to 50-µm-deep trenches for compact lateral isolation, plus an SOI substrate (silicon handle wafer with buried oxide). The cost disadvantage of this technique is partly offset by simpler processing and smaller die size (Fig. 6).
Analog foundries—modular solutions Due to these conflicting requirements, achieving high analog—digital integration levels is a significant challenge. That's because, in particular, not every application leads to high enough volume that justifies the lengthy and cost-intensive development of a new, dedicated process. Since the—one-flow-fits-all” approach is usually far too expensive, the best strategy to reconcile these demands is to opt for a modular technology approach, such as that of today's pure-play analog/mixed-signal foundries.
In conventional analog/mixed-signal approaches, only a few elements in the back-end-of-line (BEOL) processing can be added or removed to provide a small degree of customization for a standard process flow. In contrast, the high flexibility of the modular platform allows product designers to select only what they really need, even in front-end-of-line (FEOL) processing, thereby guaranteeing the best possible tradeoff between effort and performance.
Another advantage of the modular approach is the possibility of analog IP reuse, because features and models can be shared across the entire analog/mixed signal platform. This approach enables a standardized, consistent design environment that benefits both the product designer and the foundry itself, and allows the latter to provide its customers with extensive design support.
Consequently, product designers are able to develop analog libraries with a variety of—building blocks,” such as operational amplifiers, bandgaps, bias cells, analog-to-digital and digital-to-analog converters, power-on-reset generators, oscillators, and other devices that can be reused for different designs. This tremendous advantage enables foundry customers to develop large analog/mixed-signal device portfolios quickly for various applications.
Process-flow challenges The starting point for the development of a modular analog/mixed-signal platform is the CMOS digital core process with its typical process steps. To enable design IP reuse across the whole modular platform, further process steps required for the analog/mixed-signal devices must be added without losing compatibility with the core process.On the front end of the line, additional structures include deep n-wells for substrate isolation; n- and p-wells for HV and medium-voltage (MV) transistors; specially-doped (graded) source and drain regions; the poly layer; and a second or third gate oxide. At the back end of the line, steps can be added to create MIM capacitors and thick power metal or power copper options in the metallization phase.
Two main challenges must be solved to realize a fully-modular process flow architecture: maintain the compatibility between the various options and minimize the number of necessary process steps. Key compatibility elements to address include preserving doping profiles; managing the interface charges between silicon and oxide; and achieving consistent thin-film thicknesses for all oxides, as well as poly and nitride layers, for each of the possible process flows.
Depending on the number of options, advanced mixed-signal flows feature up to 25 modules. The number of different, theoretically possible process flows can reach 100,000 or more.
Doping profiles and interface charges are maintained by stringently managing the thermal budget. Some process steps require their own specific heat treatment, with precisely-defined maximum temperatures that the materials must be exposed to for a given time. More often than not, the temperatures required to create the analog structures are at odds with the baseline steps, leading to a degradation of the CMOS components.
To deal with higher voltages, special doping gradients are needed. These can only be generated by an additional heat treatment, which may lead to the disruption of existing doping profiles. To ensure full compatibility between the modules, it's essential to adhere to maximum heat treatment temperature limits. Also, thermal budgets must be maintained by running thermal dummy steps, during which the existing structures are exposed to similar temperatures necessary for the additional steps.
Thus, the modular process flow has to follow a precisely-defined sequence (Fig. 7). The HV and MV wells are created first, followed by the GOX formation steps using sacrificial etching procedures. Analog elements requiring a second poly layer need to be formed before source and drain patterning. The second challenge in process flow design—the minimization of the number of necessary steps—is addressed by reusing the HV and MV wells as much as possible for elements with different voltage requirements, such as HV, MV, and eFlash devices.
Design support challenges One crucial requirement for a high level of analog—digital integration is a comprehensive and mature design ecosystem. Digital IC design typically focuses on logical correctness, maximizing circuit density, and placing circuits so that clock and timing signals are routed efficiently. It's highly automated, at least for technologies above 130 nm, and leads to variable, fab-independent netlists and easily-generated layouts.
Analog/mixed-signal design includes a much larger variety of primitive devices. It has to cope with complex specifications, since it's more concerned with the physics of the devices—parameters like gain, matching, power dissipation, and resistance. As a result, it usually leads to fab-specific designs (Fig. 8).
Although digital designs typically are right the first time, analog designs require more iterations. To keep those to a minimum and speed up time-to-market, it's essential to carefully characterize and model the analog devices, with models reflecting all of the different operating conditions and covering all aspects impacting performance. In analog/mixed-signal design, every aspect of the design flow must be controlled as closely as possible. Moreover, model performance is crucial for the creation of reliable, high-yielding circuit designs that entail only a minimum of iterations.
In order for its fabless customers to effectively penetrate the analog/mixed-signal market, the foundry must provide a sophisticated design ecosystem that includes support for all major EDA platforms, correct models, design kits, and digital and analog IP. Using such an optimized design flow, customers can control all aspects of their analog/mixed-signal design in close cooperation with the foundry. As a result, they can use design-for-manufacturability (DFM) methodology to improve the functional yield, parametric yield, or reliability of their designs—targeting first-time right design for complex analog/mixed-signal applications (Fig. 9).
For the design-entry stage, the analog/mixed-signal foundry thus has to provide not only digital I/O and standard cell libraries optimized for power, speed, and/or area, but also a large variety of libraries for active and passive primitive devices. The following pre-layout simulation requires highly accurate models of all active and passive devices that have to include quasi saturation effects for HV, noise (1/f, noise figure, thermal noise), and RF behavior. Subsequently, a wide range of statistical models must be made available, such as worst-case models, statistical corner models, and Monte Carlo mismatch models to enable circuit design sizing and design centering techniques to achieve high-yielding robust designs.
Extensive verification routines are crucial in the design flow to guarantee the functionality, manufacturability and reliability of the analog/mixed-signal design. These verification routines must include safe-operating-area (SOA) checks for HV MOS transistors, pre- and post-layout parasitic extraction, design rule checks (DRCs), layout-versus-schematic (LRS) routines and electrostatic discharge (ESD) checks.
In addition, the foundry has to support a wide range of EDA platforms so that designers can choose the best-in-class tools that allow them to optimize their design flows. Setting up such a comprehensive design-support service requires lots of work, especially due to the complexity and difficulty of accurately characterizing and modeling analog devices. But only with such a high-quality, full-fledged design ecosystem is it possible for the pure-play analog/mixed-signal foundry to optimally serve its fabless and fab-lite customers.
An expanding business model on the rise Not many foundries in the analog/mixed-signal market have succeeded in creating such a modular platform with maximum design flexibility, i.e. the possibility to add various modules without losing the compatibility to both the core CMOS process and the other modules. The modular approach has been implemented at different technology nodes ranging from 1 µm down to 0.18 µm (Table 5).
By combining this modular scheme with a comprehensive design-support ecosystem, these pure-play analog/mixed-signal foundries open up new vistas for fabless and fab-lite companies. Otherwise, up to this point, these companies have played only a minor role on the analog market traditionally dominated by the IDMs. By helping their customers create large device portfolios of robust, high-yielding analog/mixed-signal designs efficiently and quickly, the foundries enable those fabless and fab-lite companies to successfully establish themselves on par with IDMs in the analog/mixed-signal market.
Volker Herbig, technical marketing manager responsible for strategic business model development at X-FAB Silicon Foundries, holds a master's degree in physics from Humboldt University, Berlin, Germany. He can be contacted at [email protected]