Electronic Design

Buffer IC Uses Analog Techniques To Extend Two-Wire Buses

The IES5501 two-wire bus buffer IC from Hendon Semiconductors has entered full production. One of the members of the IES550x family of bus buffers, the IES5501 is designed for extending and expanding I²C, SMBus, PMBus, IPMB, and similar two-wire bus systems. The use of analog IC design principles for a digital bus provides the IES5501 with low I/O offset voltages that allow the IC to be cascaded or daisy-chained, thus simplifying the design process. The chip’s low noise susceptibility and wide allowable voltage range make it easier to create larger bus networks without exceeding the maximum permitted bus capacitance.

The IES5501 extends the bus load limit by buffering the clock (SCL) and data (SDA) lines. Typical applications include two-wire buses in telecommunications systems (including ATCA), CompactPCI, VME bus systems, RAID products, power management systems, backplane management systems, bus switch/multiplexing buffering, and for bus voltage-level translation. The IES5501 significantly increases system noise margins on the Intelligent Platform Management Bus (IPMB). The application or removal of power to the device does not interfere with other bus activity. The IES5501 comes in RoHS-compliant 8-pin SO and 8-pin MSOP packages. For additional information, go to www.bus-buffer.com.

TAGS: Intel
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