Practically every operation within an electronics system happens in synchronisation with a clock signal. Instuctions inside a microprocessor are processed step by step to the beat of the system clock, the latest generations performing billions of operations per second.
For example, Global Positioning System (GPS) devices operate in synchronisation with recovered satellite clock signals. Without this synchronisation, satellites could not determine a vehicle’s position, and the navigation system would fail to operate correctly.
Timing devices are everywhere, making many activities we take for granted in our daily lives possible. Every time we make a phone call, send an e-mail, watch the sports channel, or withdraw cash from an ATM, we rely on precise clocking components controlling and synchronising every operation.
Not suprisingly, complex electronic systems have sophisticated clocking requirements. High-performance components require clock solutions that can provide sub-picosecond jitter performance. A typical board with data converters, FPGAs, and RF components requires several different clock frequencies that typically must be synchronised in some manner.
The required system clock performance (jitter, phase noise, spurious tones) is determined by the most demanding components—generally RF devices such as mixers and demodulators and the analog-to-digital converters (ADCs). Developing a complete clocking solution is a significant challenge for a system designer, and many companies have dedicated teams solely responsible for this task. High-sample-rate ADCs require sub-picosecond RMS jitter levels to maintain optimal noise performance.
Synchronising clock signals is challenging, particularly as signal frequencies increase. Components are often placed on opposite sides of a board or even on different boards, making distribution of synchronisation signals extremely challenging. In addition, a complex board may require several different clock frequencies and logic signal levels, low-voltage positive emitter coupled logic (LVPECL), low-voltage CMOS (LVCMOS), low-voltage differential signaling (LVDS), and other factors.
Clock Jitter Requirements For ADCs
Using the National Semiconductor ADC12D800RF 12-bit, 800-Msample/s to 1.6-Gsample/s, 2.7-GHz analogue input bandwidth ADC, let’s examine the clock jitter requirements required to meet its stated datasheet specifications. This ADC is part of a new 500-Msample/s to 3.6-Gsample/s family designed for direct RF sampling (Fig. 1).
The ADC12D800RF can achieve 56.4-dB signal-to-noise ratio (SNR), measured in the entire Nyquist band, when sampling a 1498-MHz signal. As the desired signal bandwidth is often much smaller than the Nyquist bandwidth, digital filtering can be employed to take advantage of the very low noise floor for this ADC, which is at –152.2 dBm/Hz. Its third-order intermodulation distortion (IMD3) is –87 dBFS at FIn = 2670 MHz ±2.5 MHz at –16 dBFS.
There is a direct correlation between the accuracy of the sampling clock and the dynamic performance of an ADC. Timing uncertainty or jitter will have an impact on the SNR. Harmonics of the sampling clock will also mix with the analogue input, resulting in reduced IMD and noise power ratio (NPR) performance. Therefore, a low-jitter clock source with excellent spurious noise performance is required.
If the input voltage is optimised to equal the full-scale range of the ADC, the jitter requirement becomes a factor of the ADC’s input noise floor and the input frequency being sampled. Assuming the entire Nyquist band is used, in which case SNR reflects the ADC noise floor integrated over the Nyquist band, the following equation can be used to calculate the required jitter to meet a desired noise specification:
Tj = (2πFIn10SNR/20)–1
where Tj = RMS timing jitter and FIn = analogue input signal frequency.
This is a well-known equation. While it was derived for a sinusoidal input at the ADC, it still provides a reasonable estimate of SNR for a broadband signal if the sample rate is significantly higher than the signal bandwidth.
The SNR due to jitter is independent of ADC resolution and sample rate, and it decreases as the signal frequency increases. For an input frequency of 1498 MHz, the total jitter requirement to meet an SNR of 56.4 dB is 160 fs. Let’s look at timing devices capable of delivering this level of performance.
Timing devices are used to generate one or more clock frequencies from a given reference clock. Sometimes this reference clock may have excellent spectral purity and the function of the clock conditioner is to distribute this frequency, or some multiple of this frequency, throughout the system. This is a clock multiplier application.
In other situations, the reference clock signal has poor spectral purity, and the function of the clock conditioner is to clean up this signal. This is a jitter cleaner application. It is also possible that the clock conditioner could perform both functions simultaneously.
The distinguishing characteristic of a precision clock conditioner is the noise performance. Because clocks typically are used to provide a means for synchronising events in a system, the ability to control and minimise skew and achieve well-aligned clocks is also a very useful feature. Timing devices that integrate all this functionality are often called clock conditioners (Fig. 2).
National Semiconductor’s LMK04800 clock conditioner features the dual-loop PLLatinum architecture, which comprises two high-performance phase-locked loops (PLL), a low-noise crystal oscillator circuit, and a high-performance voltage-controlled oscillator (VCO) to enable excellent jitter performance.
The first PLL (PLL1) provides a low-noise jitter cleaner function while the second PLL (PLL2) performs the clock generation. PLL1 can be configured to work with either an external voltage-controlled crystal oscillator (VCXO) module or the integrated crystal oscillator with an external tunable crystal and varactor diode.
When used with a very narrow loop bandwidth, PLL1 uses the superior close in phase noise (offsets below 50 kHz) of the VCXO module or the tunable crystal to clean the input clock. The output of PLL1 is used as the clean input reference to PLL2, where it locks the integrated VCO. The loop bandwidth of PLL2 can be optimised to clean the far-out phase noise (offsets above 50 kHz) where the integrated VCO outperforms the VCXO module or tunable crystal used in PLL1.
The LMK04800 family features two clock inputs with redundancy, 14 differential clock outputs, and default clocks upon power-up. The input block is equipped with holdover and automatic or manual selection of the reference clock. Also, six blocks consisting of a programmable divider, a phase synchronisation circuit, and programmable delays drive 12 output clocks. All VCO driven outputs have a programmable LVDS, LVPECL, or LVCMOS output buffer.
National Semiconductor has developed a clock design tool that can be downloaded from its timing solutions Web page and used offline, if desired. The tool aids the selection of a timing device and helps users design a loop filter for optimum phase noise/jitter for their selected solution.
The software in “wizard mode” can auto-calculate VCO frequency and divider values for PLL and output dividers to achieve the specific frequency requirements as entered by the user. Once wizard mode is selected, the required user-defined inputs include the architecture type (designs with a single PLL or two PLLs in series), a reference and/or VCXO1 definition (optional), and output frequency and type definition.
Once defined, two additional steps are required:
- Select solution: Select from the devices that satisfy the design requirements.
- Select desired configuration: There may be several possible solutions depending on requirements. The program will automatically highlight the optimum solution/configuration based on internal calculations.
Once the simulation screen has been reached (Fig. 3), users then will be able to:
- Calculate loop values for loop filters
- Update phase noise profiles for blocks like oscillators and VCXOs
- View RMS jitter measurements of available outputs
- Copy phase noise simulation traces to clipboard for pasting into Excel or other programs
- Save the design
The tool was used to select a device for generating an 800-MHz LVDS clock for the ADC12D800RF, and it selected the LMK04806B (Fig. 4). The total RMS jitter integrated from 1 kHz to 10 MHz is 109.1 fs. As calculated previously, this is well within the required range needed to meet 56.4-dB SNR at 1498 MHz. The remaining differential and single-ended outputs can be configured for all other system clocks.