Many complex video, audio, and telephony systems require electronic signals to arbitrarily switch within a given network of M inputs and N outputs. There are important trade-offs to consider, however, when selecting a CMOS or bipolar crosspoint-IC solution.
The common belief that CMOS is inherently lower in cost and power when compared to bipolar is no longer true, particularly in video applications. The designer must consider the total solution cost of each approach before proceeding with a design. In most applications, all inputs and outputs of a CMOS crosspoint IC need to be buffered. Bipolar ICs already have these buffers integrated into the die.
To minimize the effects of crosstalk and signal-frequency roll-off, consider the layout of the board. Multilayer pc boards are usually required to maintain a characteristic impedance, as well as to isolate and shield multiple signal paths from generating or receiving interference signals.
In years past, switching was accomplished by connecting a matrix of inputs and outputs, either manually or by using electromechanical devices. These switching networks were often referred to as a "crossbar switch," or in more modern times, as a "crosspoint switch."
With the advent of semiconductors, crosspoint-switching arrays were made using discrete transistors. Later, ICs were utilized, particularly with analog multiplexers. Over time, these techniques became costly and sometimes unreliable. Today's design is simplified by using monolithic crosspoint-switch ICs already designed with an M-by-N matrix size and configuration-state storage in digital registers. Most crosspoint-IC logic can be programmed with serial or parallel data to set the required connection of inputs to outputs. Thanks to these components, it's now possible to design cost-effective crosspoint-switch arrays using single or multiple crosspoint ICs that have excellent performance and reliability.
Bipolar vs. MOS Crosspoint Switches: The first solid-state crosspoint solutions available on the market were manufactured using MOS processes. CMOS or DMOS are commonly used processes. Originally targeted for audio and telephony applications, these devices are still in use. A basic MOS crosspoint is designed with the well-known "T-switch" cell (Fig. 1), which is essentially a NMOS 2:1 multiplexer consisting of T switches S0 and S1. Its advantages lie in its simplicity, zero dc offset, low-static power dissipation, and cost. Since the inputs and outputs of the switches are symmetrical, the switch is inherently bidirectional, which is essential in many telecommunication applications. In effect, the bidirectional design connects the input source to the load when the switch is on, limiting the number of outputs to which an input can be fanned out. This bidirectional signal path is formed by the inherent RDS-ON resistance from input to output. The magnitude of RDS-ON in the pass transistors (M1 to M4) depends on the voltage level of the applied signal. Figure 1b shows the nonlinear relationship between RDS-ON and signal voltage.
To minimize this effect, T switches are designed using a CMOS process (Fig. 2). The model is approximated by a three-pole low-pass filter where CS and CD are the source and drain capacitance in the on state. CMOS lets complementary transistors (M1´ to M4´) be added in parallel with M1 to M4, helping mitigate the nonlinear affects of RDS-ON on the signal. The transfer functions of the complementary transistors "overlap" each other, aiding to minimize RDS-ON and improve the switch linearity (Fig. 2b). This tends to reduce the level of dc errors and ac distortion in the T switch.
Typically, to get RDS-ON as low as possible, very large devices are required for each CMOS transistor. This often results in a large input capacitance of ~10 pF, a high-disable output capacitance of ~10 pF, and a substantial charge injection of ~5 pC when switching between channels. If not properly compensated, the consequence of the charge injection can be large glitches of ~1 V. Compensation for some of these shortcomings can be achieved by shrinking the switch transistors and buffering the inputs and outputs on the die.
Unfortunately, CMOS processes aren't well suited for implementing high-performance, analog-buffer amplifiers. Crosspoint ICs designed using CMOS generally don't include drivers (gain) to operate directly into the back-terminated connections used in telecommunication and video applications. Designers using CMOS crosspoint switches must use external buffers on the inputs and outputs to alleviate RDS-ON effects and charge-injection-induced glitches, as well as to drive back-terminated loads. The designer must consider buffers and drivers with specifications to drive large capacitive loads up to 100 pF, with little degradation in frequency response and distortion. This requirement adds cost and power consumption to the design, while complicating the pc-board layout and assembly.
Crosspoint-IC solutions are available for more demanding applications like composite video and computer graphics, which have integrated buffers and drivers. These are fabricated using a fast complementary bipolar process with efficient vertical NPN and PNP transistors that are well matched. One particular process that is well suited for these applications is Analog Devices' eXtra Fast Complementary Bipolar process (XFCB), based on silicon-on-insulator (SOI) using bonded wafers. This process not only allows for small- geometry transistors, but supplies extremely fast performance with low supply currents and voltages (±5 V).
Figure 3 shows the schematic of a complementary bipolar, switched- transconductance (GM) switch. This is essentially a simple buffered 2:1 multiplexer. In this architecture, a current-mode decoder selects one of two transconductance input stages (GM0 and GM1) by steering it to a fixed current, IO. The output of the selected GM is a differential current that's converted to single-ended current by mirror Q5/Q6, and integrated by C1 and the high-gain stage, A1. The buffered output (G = +1 block) of A1 is used as a common feedback voltage for all of the input stages, in this case IN0 and IN1. The high loop gain of the gm switch minimizes the error between the selected input and the output. Unlike the CMOS T switch, the bipolar switch has a unidirectional signal path from input to output, with a high input impedance. Its enabled output impedance (~ 0.2 Ω) is virtually signal-level independent and much lower than that of a CMOS switch (typically 10 Ω).
Ideally, inputs applied to unselected GM stages don't influence the output. Yet parasitic capacitance, due to internal devices and external wiring, can act as high-pass conduction paths between the unselected inputs and outputs. Careful layout can reduce, but not entirely eliminate, the coupling due to wiring parasitics. In a large, switched-GM crosspoint array, the length of the common output lines shared by the collectors of the input devices exacerbates unwanted coupling. Rejection of this type of crosstalk is improved in this topology because common-mode coupling to these lines is rejected by the differential-to-single-ended converter. Circuit techniques to reduce pc-board layout- induced crosstalk will be covered later in this article.
Bipolar switch parasitics aren't as large as the RDS-ON and drain/source capacitance in a properly sized MOS switch. And, the effect on bandwidth due to output fan-out is minimized. In addition, the complementary-bipolar process lets high-performance buffers (either unity gain or gain of two) be integrated into the crosspoint-IC chip. In certain applications, this gives distinct performance and cost advantages over MOS solutions, which require separate buffers at the crosspoint inputs and outputs. The disadvantage of the bipolar switch is a higher quiescent current compared to a MOS switch, as well as the switch being unidirectional.
For most audio and telephony applications, the operational bandwidth is < 100 kHz. Thus, MOS solutions (with their low bandwidth, cost, and inherent bidirectional operation) are well suited for these applications. Furthermore, these devices are fabricated on high-voltage processes suitable for telephony applications.
Video and analog computer graphics applications require higher bandwidth in the range of 4 MHz to 100 MHz or greater, with signal levels less than 2 V p-p. Bipolar ICs are better suited for these applications because of the small parasitics and integrated buffers in the inputs and outputs. These advantages make it possible to design large, cost-effective crosspoint arrays up to 1024 by 1024 using numerous bipolar crosspoint ICs. Due to the inherent parasitics and bandwidth limitations of MOS crosspoint ICs previously discussed, MOS solutions are severely compromised in forming arrays larger than 256 by 256. Consequently, designs of large arrays with MOS crosspoints in high-speed applications, like video, are compromised in key performance areas like bandwidth and differential gain/phase.
A common misconception exists around the cost of MOS solutions compared to bipolar solutions for crosspoint ICs, particularly in video, graphics, and datacom applications. Some designers' first impression is that MOS-based solutions should be inherently lower cost than bipolar. This turns out to be no longer true, particularly with CMOS solutions. As shown, bipolar crosspoint switches have nearly an order of magnitude higher useable bandwidth over CMOS solutions (Fig. 4). Secondly, the bipolar crosspoint can have video-grade buffers and drivers integrated into the device die. Due to the difficulty of making high-grade analog buffers, this isn't possible in CMOS. Consequently, bipolar crosspoints can literally be used "as is" in creating arrays of nearly any size, whereas a CMOS crosspoint requires extra buffer components on the inputs and outputs. And, when trying to produce larger crosspoint arrays, a CMOS crosspoint also suffers from being severely limited in bandwidth.
Creating Larger Crosspoint Arrays: As stated, there are trade-offs in selecting the right crosspoint-switch technology for a given design and application. Equally important are the design considerations when applying a crosspoint IC, particularly in creating large crosspoint arrays and systems. Because arrays larger than 16 by 16 (256 connections) typically use multiple crosspoint ICs, various errors and tolerances present in an individual IC will compound themselves. The first step is to select the largest crosspoint-IC array, offering performance in excess of the ultimate system specification. This can save significant design time and product cost, because much of the art of designing well-performing crosspoint systems involves devising compensation schemes. These schemes work around device limitations to meet overall system specifications.
Many systems require critical IC performance parameters to match, at least to some degree, from channel to channel, and not vary excessively as the crosspoint is programmed to different configurations. This can require significant experimentation to find the right combination of components and board layout that produce the desired performance.
For example, a bipolar 16-by-16 crosspoint IC, like the AD8114/15, can eliminate one tier of design effort required for a larger system. This contrasts using 64 4:1 multiplexer devices, or four 8-by-8 MOS crosspoints with 32 extra buffers.
Typical parameters that may require fine-tuning are bandwidth, dc offsets, crosstalk, channel-path delays, and differential gain/phase. The bandwidth will roll off as more devices are cascaded in a channel, while the dc offsets and differential gain/phase will vary as the square root of the number of cascaded devices. While most of these parameters are a direct function of component specifications, crosstalk can be further complicated by pc-board layout, and in general will increase as the system dimensions increase.
Crosstalk: Systems with multiple analog signal channels, such as broadcast video, have strict requirements for crosstalk, or the presence of an undesired signal from one channel to another channel. This is a major design challenge, because all of the inputs and outputs in a crosspoint system must be brought in close proximity to make the interconnections. In virtually all crosspoint systems, keeping crosstalk to a minimum is critical.
Crosstalk comes from three major mechanisms: an electric field that is coupled by capacitance, a magnetic field coupled by mutual inductance, and current through a common impedance that is shared by two channels. In all cases, crosstalk becomes more difficult to control as the signal frequency increases. Common techniques used to prevent crosstalk consist of circuit shielding and separation, component bypassing, and careful signal routing.
Capacitively coupled crosstalk can occur between two or more conductors. From a circuit standpoint, the crosstalk mechanism looks like capacitive coupling to a resistive load at the input of a crosspoint IC. For low frequencies, the magnitude of the crosstalk is given by:
Crosstalk = 20 log10 \[(RSCM) * s\]
where RS is the source resistance, CM is the mutual capacitance between the signal circuits, and s is the Laplace transform variable.
Take, for example, two input channels into a crosspoint-switch IC. From this equation, it can be observed that this crosstalk mechanism has a high-pass nature. It also can be minimized by reducing the coupling capacitance of the input circuits. This can be done by using crosspoint devices with a ground or power supply pin between the signal pins to provide shielding against crosstalk. This is a standard pinout in Analog Devices' crosspoint ICs. A pc-board designed for low crosstalk should have the signals routed, as much as possible, on inner layers with ground planes above, below, and in between traces on the signal routing layer.
Crosstalk also can be induced between two conductors, when large drive currents are required in loads such as 150-Ω video applications. From a circuit standpoint, this crosstalk mechanism looks like a transformer with a mutual inductance between the windings that drives a load resistor. For low frequencies, the magnitude of the crosstalk is given by:
Crosstalk = 20 log10 (MXY * s/RL)
where MXY is the mutual inductance between two conductors and RL is the load resistance on the conductors.
By increasing the spacing of the conductors and reducing their parallel length, the effects of inductively coupled crosstalk are minimized. When this isn't possible, or more crosstalk reduction is required, copper shielding of the field lines generated by current in the conductors can be employed. This will block the penetration of these magnetic flux lines by generating localized eddy currents in the shield material, minimizing their coupling to other conductors.
Pc-Board Layout: Extreme care must be exercised to minimize additional crosstalk generated by the system circuit board(s). Areas that must be carefully considered include grounding, shielding, signal routing, and supply bypassing. In component selection, as stated earlier, it's important to choose a crosspoint IC with a ground or power-supply pin between signal pins to provide shielding right up to the IC package. These ground and power-supply pins should be tied to a large plane with as low an impedance return path as possible.
One technique to mitigate the effects of capacitively and inductively induced crosstalk is to use multilayer pc boards for circuit layout. In this case, circuit separation can be accomplished in a vertical direction, as well as horizontally. Furthermore, space is available to route ground planes between signal circuits to lower the effective impedance of these traces, as well as to provide shielding. An example of a four-layer, pc-board layout for signal circuits is shown in Figure 5.
This illustration shows the important dimensions to consider in designing a pc-board signal trace to a characteristic impedance. For example, video applications require a characteristic impedance of 75 Ω. To calculate the dimensions, use this equation:
where ER is the dielectric constant of the pc-board material.
Note that unused regions in the four layers should be filled with ground planes. Then, in addition to having controlled impedances, the input and output traces also will be well shielded.
Signal paths in most systems generally share a common return path or ground. Signal current into this finite impedance path can interact with other signals and cause crosstalk. To avoid this, take care in the layout to minimize the signal-path ground impedance. Doing so will ensure that return-path currents minimally interfere with the signals. Use commonly connect ground planes with the lowest impedance possible to accomplish this.
The power supply also can be a source of crosstalk. When an active device drives a signal channel, the consumed current can create interference reflected back into the power supply. This interference results from current in the impedance of the power-supply circuit. Any channel that shares this power supply will be subjected to this interference signal, which will induce crosstalk. Bypassing the power supplies—as close to the crosspoint devices as possible—with good high-frequency capacitors will help reduce this effect. Typically, a 0.01-µF capacitor is a good choice for high-frequency applications.
Design/Evaluation Tools: Nearly all suppliers of crosspoint ICs provide components mounted on evaluation boards. A good board will minimize the layout and signal routing difficulties discussed above. This allows the designer to fully evaluate the performance of the device itself, with minimal errors due to layout.
Lastly, the vendors' web sites can be a source of additional design information. For example, http://www.analog.com/high-speed-switches contains data sheets, white papers, and applications notes. Such information aids the designer in selecting crosspoint IC components, while helping them avoid deep design pitfalls.