Electronic Design

Cutting-Edge Breakthroughs Expand ADC Boundaries

From the frigid wastes of 4.2 Kelvin to torrid conversion rates in the gigasample/s range, the analog-to-digital converters revealed at this year's ISSCC and elsewhere can adapt to new challenges.

Analog-to-digital converters (ADCs)—the workhorses of the industry—have plowed their way through applications like industrial process control, medical instrumentation, communication systems, and radar for decades. Continual increases in performance specs have kept these blue-collar devices in step with the latest advances.

February's International Solid State Circuits Conference (ISSCC) in San Francisco presented the cream of the ADC crop. A number of papers on the Nyquist Track redefined the state of the art, while two pushed into new territory. And, let's not forget the latest announcements from the usual suspects.

"A Cryogenic ADC Operating Down to 4.2K" from IMEC and KU Leuven describes a successive approximation register (SAR) ADC for applications down to 4.2 Kelvin, a temperature where transistors work differently from what most of us are used to. The chip is an 8-bit SAR implemented in a conventional 0.7-mm CMOS technology. Its sampling rate is 3 kHz. At 5 V, it consumes 350 mW for a 300-pF load capacitance.

"Low-temperature detectors for X-ray and far-IR imaging and spectroscopy for space exploration and particle experiments require proximity electronics also cooled to deep cryogenic temperatures," the paper says. "Cryogenic ADCs would improve signal integrity between cold and warm electronics."

The problem with operating at cryogenic temperatures is a phenomenon called "carrier freeze." Below 77 K, a level where CMOS performs better than at normal temperatures, problems include hysteretic irregularities in the I-V transfer characteristic, including a negative transconductance region (Fig. 1).

The authors used quasi-empirical design methods to create a CMOS ADC functional between ambient temperature and 4.2 K. They simulated its low-temperature characteristics with Spice, using parameters extracted from cryogenic transistor measurements. Their chip comprises "a capacitive DAC (digital-to-analog converter), a charge-transfer preamplifier (CTA), a latched comparator, and an externally set-table SAR" (Fig. 2).

According to the authors, "While cooling the ADC from ambient temperature down to 4.2 K, no instabilities or hysteresis induced by the low temperature are observed. The INL (integral nonlinearity) increases from 0.5 to 20.8 LSB (least significant bit) and the DNL (differential nonlinearity) from 0.4 to 1.1 LSB."

In "A 50GS/s Distributed T/H Amplifier in 0.18 mm SiGe BiCMOS," authors from Alcatel-Lucent present a 50Gsample/s distributed track-and-hold amplifier (DTHA) based on a distributed topology. Addressing the pressure for increased sampling rates in high-bit-rate optical transceivers and millimeter-wave radios, they created the three-stage DTHA using distributed microstrip lines to enhance bandwidth. The amplifier exhibits a spurious-free dynamic range (SFDR) better than 40 dB.

"The DTHA has a lumped input buffer consisting of an emitter-degenerated differential amplifier preceded by a pair of emitter followers. The input has 50-V on-chip resistors to provide a good input match. The input buffer provides unity gain and very low output impedance to drive the distributed switched emitter followers and output buffer (SEFOB) stages," the paper says.

"To avoid multiple reflections between the input buffer output and the termination of the distributed SEFOB input line, the differential amplifier has load resistors of 50 V, which approximately match the image impedance of the distributed SEFOB stage. Active current sources are used for all building blocks to enhance the CMRR (common-mode rejection ratio) at low frequencies and provide a more flexible way to modulate the current," it notes.

"The distributed SEFOB stages consist of three identical SEFs and output buffers connected by balanced microstrip transmission lines," the paper continues. "The clock distribution is the most important factor to account for sampling jitter... \[A\] cascode architecture is used to decrease the capacitive loading of the output and to minimize the bandwidth degradation caused by Miller capacitance... The distributed output stage generates the sequence of ‘Track' and ‘Hold' control signals for the SEFOB cells."

During ISSCC's delta-sigma track, ADC designers revealed advances in dynamic range and power consumption. For example, "A 56mW CT Quadrature Cascaded SD Modulator with 77dB DR (dynamic range) in a Near Zero-IF 20MHz Band" from NXP/Philips describes a cascaded delta-sigma modulator with continuous-time (CT) quadrature loop filters (Fig. 3).

"The first stage consists of the quadrature loop filter QLF1, A/D converters ADC1i and ADC1q, and feedback D/A converters DAC1i and DAC1q. The quantization error, Qi+jQq, of the first stage is obtained by feeding digital outputs Y1i and Y1q to D/A converters DAC2i and DAC2q, respectively, and subtracting their outputs from the inputs of ADC1i and ADC1q," the paper says.

"This quantization error signal, Qi+jQq, is then fed to a second cascaded stage comprising loop filter QLF2, A/D converters ADC2i and ADC2q, and D/A converters DAC3i and DAC3q. The digital outputs of the two stages both contain the quantization error Qi+jQq, but with different transfer functions. Therefore, the second stage output is fed to a digital quadrature noise-cancellation filter (QNCF) in order to match both transfer functions.

"Subtraction of the QNCF output from a delayed version of the first stage digital output cancels out Qi+jQq. The resulting signal Yi+jYq has very little quantization noise in the band of interest. Finally, a quadrature decimation filter (QDF) filters off the out-of-band quantization noise," the paper concludes.

Turning to other architectures, "A 10b 160MS/s 84mW 1V Subranging ADC in 90nm CMOS" proposes that subranging ADCs are ideal for mixed-signal ASICs. Written by Huber, et al., at UCLA, it describes a 10-bit, 160-Msample/s sub-ranger (5-bit coarse ADC, 6-bit fine ADC, with associated preamps and comparators) with an integral THA.

The prototype consumes 84 mW at 1 V and achieves better than 9.1 equivalent number or bits (ENOB) and 75-dB spurious-free dynamic range (SFDR) across the full Nyquist band, retaining 8.5 ENOB and 7-dB SFDR to 200 MHz. In the design, the coarse ADC and fine ADC sampling switches are clocked on opposite clock phases, which increases fine ADC latency by 1/2 clock period. This gives the coarse ADC time to perform its quantization.

Another group from UCLA teamed with Realtek in Taiwan to present "An 11b 800MS/s Time-Interleaved ADC with Digital Background Calibration." The paper details a time-interleaved ADC design for 10GBaseT (IEEE 802.3an) 10 Gbits over twisted-pair applications. Such an ADC must handle 800 Msamples/s, with a 400MHz bandwidth and an ENOB greater than 9 bits.

Accomplished in 90-nm CMOS, the design uses four interleaved pipelined sub-ADCs that sample at 200 MHz, digital calibration logic, reference-voltage buffers, and a clock generator. It includes an op-amp-sharing technique between sub-ADC pairs. Each sub-ADC consists of 12 1.5-bit/stage multiplying DACs to generate 13-bit outputs, with two extra bits for calibration.

The prototype consumes approximately 12 mW. At a sampling rate of 800 MHz, the DNL and INL were less than 0.5 and 1.6 LSB, respectively. The signal-to-noise plus distortion ratios (SINADs) after calibration were 58 and 54 dB for 15- and 400-MHz inputs, respectively.

Linear Technology's LTC2285 is a dual, 14-bit, 125-Msample/s, low-power, 3-V ADC for digitizing high-frequency, wide dynamic range signals. It's designed for WiMAX basestations, where its high data rate will double what is now achieved with standard 62-Msample/s converters.

Its ac performance specs include 72.2-dB SNR and 82-dB SFDR at Nyquist. Typical dc specs include 61.5-LSB INL and 60.6-LSB DNL. Transition noise is 1.3 LSB(rms). The chip runs off a single 3-V supply, but a separate output supply allows the outputs to drive 0.5- to 3.6-V logic. Sampling now, production quantities are slated for September. Pricing will start at $73.50.

For similar applications, Analog Devices' AD9640 dual, 14-bit ADC samples at rates beyond 135 Msamples/s. Its SNR is 72.7 dBFS and SFDR is 85 dBc with a 70-MHz intermediate frequency. (It can support IFs as high as 450 MHz.) To simplify clocking and reduce jitter, the AD960 includes its own clock divider, enabling it to run off the same clock used by the basestation's DACs.

To simplify automatic gain control (AGC), the chip includes two circuits. One is a block that monitors the incoming composite signal power and generates a slow-response gainup/gain-down signal. The other provides a fast-detect (FD) mode that can detect an input over-range condition in as little as two clock cycles, immediately reducing the gain to avoid overdriving the analog front end.

The AD9640 comes in 12- and 14bit resolutions with sample rates of 80, 105, 125, and 150 Msamples/s. The 14-bit versions cost between $37.50 and $87.50.

Late last year, Texas Instruments unveiled a 12-bit, 500-Msample/s pipeline ADC with 64.5-dBFS SNR and input-frequency specs up to 500 MHz at the full conversion rate. The ADS5463 delivers 84-dBc SFDR and 10.5 ENOB while consuming 2.25 W. Pricing starts at $125.

In January, TI introduced the ADS5547 and ADS5527. These 14and 12-bit, 210-Msample/s ADCs are now the top performers in the ADS55xx pin-compatible, high-speed family. They provide up to 73.3-dBFS SNR and 85-dBc SFDR at a 70-MHz input frequency.

One unusual feature is that in both the low-voltage differential signaling (LVDS) and CMOS output modes, the output clock can be moved around its default position. This can be accomplished via a package pin or via the serial interface. Shifting the clock allows for tradeoffs between the setup and hold times. It's also possible to align the output clock edge with the data transition. Prices for the ADS5547 start at $82.50 each.

One of the more striking things about the ADS5547 is the use of color in the product datasheet to show performance contours (Fig. 4). The note that goes with the contour plots says: "All plots are at 25°C, AVDD = DRVDD = 3.3 V, sampling frequency = 210 MSPS, sine wave input clock, 1.5 VPP differential\clock amplitude, 50% clock duty cycle, 21 dBFS differential analog input, internal reference mode, 0 dB gain, DDR LVDS data output (unless otherwise noted)."

National Semiconductor also has announced a 16-member family of pipeline ADCs, led by a 14-bit, dual 105Msample/s chip with serial LVDS outputs. Typical performance numbers include a 72-dB SNR and 83 db of SFDR at a 240-MHz input. The family consists of single and dual 12- and 14-bit converters with sampling rates from 65 to 105 Msamples/s. Pricing for the top-of-the-line ADC14DS105 starts at $82.35.

Coming in at the high end of sampling rates, National has introduced an eight-bit, ultra-high-speed ADC family based on its existing folded/ interpolated architecture, which delivers 6-Gsample/s data capture at 3.6 W. (That's based on interleaving a pair of 3-Gsample/s ADC0-83000 ADCs, which is facilitated by the lack of need for additional clock adjustment circuitry.) Full-power input bandwidth of the ADC083000 is 3 GHz.

In the same architecture, National introduced the ADC0B83000, which combines the 3-Gsample/s sampling of the "non-B" version above with a programmable 4-kbyte memory buffer. The part was developed for radar and light-detecting and ranging (lidar) applications, where the data is captured in bursts and transferred at lower data rates.

The basic ADC083000 without the buffer has 3-GHz, full-power bandwidth. Thus, it can sample wideband signals even in the second Nyquist band. By adjusting sampling clock phase on-chip, designers can interleave multiple ADCs on a board without external clock-adjustment circuits. The converter provides standard 1:4 demultiplexed outputs for simplified data capture or a new 1:2 output mode for reduced pin count. It also supplies test patterns on the outputs for system design and test.

Typically, the ADC083000 hits 7.0 ENOB, 44-dB SNR, and 54-dB SFDR when sampling a 750-MHz input at 3 Gsamples/s. After sampling, the version with the buffer (the ADC08B3000) stores the data in a 4-kbyte FIFO. One or two 8-bit CMOS output buses then transfer data from the FIFO out of the ADC to the processor at slower rates. Top speed is 400 Mbytes/s. The ADC083000 costs $523 in 1000-unit lots.

For more, see "Differentiation And The Industrial Market", and "CT Delta-Sigma Experience".

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