Narrow-band low-frequency power-line communications (NB LF PLC) is a hot topic these days. Engineers creating PLC modems must consider which PLC standard (PRIME, G3, S-FSK) will be used and which hardware will get the best performance out of the design.
The modem’s power supply unit (PSU) also is essential for good performance. The PSU supplies the PLC modem as well as all of the other components in the device. In PLC-enabled smart meters, for instance, the metrology part is powered from the same supply. However, the modem plays a primary role in the power supply design.
The first parameter to check is the efficiency of such a power supply over a wide load range. Reception mode, when the modem listens for the data packet at the power line, requires about 200 mW. However, the power consumption can go up to almost 3 W if the modem needs to transmit data packets into a power line with low impedance (~2 Ω).
The modem is in listening mode most of the time. It should have good efficiency at this working point. At the same time, it must be able to respond very quickly to more amps during data transmission.
The next parameter is the operating frequency of the power supply’s switching parts. Ideally, this frequency (and the first few harmonics) should not fall into the frequency region where PLC communication is performed. The NB LF PLC frequency range is 0 to 500 kHz.
While most of the world uses the entire band, in Europe the CENELEC committee has defined four bands going up to only 148.5 kHz: Cen A (3 to 95 kHz), Cen B (95 to 125 kHz), Cen C (125 to 140 kHz), and Cen D (140 to 148.5 kHz). Cen A is reserved for metering operated by utilities and their partners, while the remaining bands can be used for other kinds of applications.
Knowing the device’s end application can help identify the right parts for the PSU from the beginning. A design that allows the selection of an operating frequency by changing the values of passive components enables a common PSU for different PLC applications. Of course, working in the PLC transmission band is allowed, but additional filtering might be necessary.
Another important requirement is that the mains filter of the PSU must not attenuate the PLC signal. By nature, the PLC signal is injected at the same point the PSU is connected to the mains. If a three-phase smart meter design is planned, the design must ensure the system works even if one or two phases fail. A three-phase PLC design will listen to all three phases and drive (the same signal) into all three phases at the same time.
Constant Switching Frequency
The design introduced here fulfills all of the requirements for a PLC-compatible PSU. We cannot use a typical “Green Mode” controller, because it adapts the switching frequency (FSW) and the operating mode to the load.
For example, the UCC28600 works at high line at 130 kHz for most of the load conditions. But when the load is very small, which is the case in receive mode, the switching frequency decreases to 40 kHz to stay in “quasi-resonant” mode and prevent switching losses.
For very light loads, the frequency will be clamped to 40 kHz and the controller will enter a burst mode. The frequency variation is even wider at low line, as the controller sweeps the frequency back and forth from 40 kHz to 130 kHz.
A better choice for this converter is the LM5021, which can be configured with constant switching frequency, with or without pulse-skip mode and burst mode. Burst mode keeps the switching frequency constant inside each burst, while the pulse skipping introduces a frequency of FSW/n, where n = number of skipped pulses.
Pulse skip mode should therefore be avoided since it may generate sub-harmonics in the PLC band. Figure 1 shows the architecture of the whole PSU with the description of all outputs needed by the system.
An isolated flyback converter provides two outputs, 16 V and 5 V. The regulation is connected on both outputs, but with greater importance given to the 5-V output. The 16-V output will supply the transmitter section, which accepts 15 V to 18 V.
The 5-V section is down-stabilised to 3.3 V by means of a low dropout regulator (LDO) and feeds the microcontroller. A buck converter with a TPS62240 supplies the digital part of the load.
Flyback Converter Design
The flyback converter represents the interface to the mains and the power line communication. In typical offline flyback converters, the input filter (Filter #1) has classX capacitors connected directly between line and neutral or line to line. We want to avoid them, because they create low impedance for the PLC signal and might reduce the signal-to-noise ratio of the receiver.
An inductor should be the first component seen from the mains side, and it must have higher reactance than the PLC output impedance. A 10-Ω fused resistor is used to control the inrush current and to protect the converter in case of short circuit.
A second filter after the rectifier, like the first one, has two functions: common mode and differential mode, damped by the 10-kΩ resistors to avoid unwanted resonance in the megahertz range (Fig. 2). The equivalent LC filter is achieved by twice the inductance times the capacitor C2. The clamp network connected to the MOSFET’s drain is not the typical RCD circuit, but a diode and transient voltage suppressor (TVS) in series.
The advantage of this setup compared to an RCD network is that during burst mode, an RCD network’s clamping capacitor would dissipate energy into the parallel resistor because it would remain charged, or at least, it wouldn’t discharge itself after each burst cycle. In the diode plus TVS case, the energy is lost during the burst because there is no storage element.
This strategy added to the low startup current of the LM5021. The burst mode feature allows the flyback stage to gain efficiency at light load, even at high input voltages, which is the case for a three-phase input.
By means of an NPN transistor and a resistor, a small current is injected into the current sense pin, sufficient to disable the skip-cycle mode. If, in other applications, the power supply was allowed to take advantage of this working mode, the resistor could be open and the transistor unpopulated.
Figure 3 demonstrates efficiency with and without skip-cycle mode, showing a clear improvement in the light load efficiency. Two groups of three curves have been plotted by varying the input voltage and the load. The green lines show higher efficiency due to the skip-cycle mode, while the feature was disabled in the red curves.
Finally, Figure 4 is a photo of the prototype. It is important to note that the filter electrolytic capacitors are quite large compared to the available surface because the converter must work from 90 V ac to 460 V ac, in single-phase, three-phase, and line-to-line “delta” connection.