Electronic Design # Dither: It’s Not Just For Breakfast Anymore

When working with mixed-signal technology, you will find that the subject of dithering keeps showing up. Most engineers know that averaging “n” samples of an analog-to-digital converter (ADC) will reduce the noise by the square root of the samples averaged. This is because the signal part adds linearly while the noise part adds as the square root of the sum of the squares (Equations 1 and 2):

Sample = signal + noise                      (1) However, what if the noise level is below the quantization level of the ADC? For example, if your ADC outputs a steady 47 counts, no matter how many samples you average, the answer is still 47 (Equation 3): This is where additive dithering can help. What is needed is some waveform that has an average of zero and an amplitude at least 1 LSB of the quantization level of the ADC. The triangular dither shown in Figure 1 fits this requirement. Fig 1. When a triangular dither with a peak-to-peak amplitude of at least an LSB is added to a signal, the average of the quantized signal equals the original signal value.

For this example, an ideal ADC with 1-mV resolution is fed an 116.357-mV input. If quantized, the result would be 116 counts. But when the dither is added, the quantized result is 117 counts 35.7% of the time and 166 counts 64.3% of the time for an average of 116.357 counts (Fig. 2). Fig 2. Mixing two beating frequencies into the ADC’s anti-aliasing filter provides an inexpensive source of dither. The resistor value (475k) sets the dither amplitude.

The two square waves, with slightly different frequencies, are mixed and filtered. Together they generate a triangular waveform with the amplitude set by the logic voltage level and a frequency equal to the difference of the two square waves.

The mixed signal is capacitively coupled to make its average value zero. The series resistor sets the dither amplitude. The anti-alias filter is used to convert the digital stream to a triangular waveform. Set the sample rate to 10 ksamples/s, and you can average eight signals. Set it to 20 ksamples/s, and you can average 20 samples.

Dither With DACs

I’ve never been much concerned about the resolution of digital-to-analog converters (DACs) when generating ac signals because I can always compensate for lack of resolution by oversampling and filtering the output.

For example, when generating a 1-kHz sinusoid with an 8-bit, 1-Msample/s DAC, all the quantization noise will be at frequencies 1 MHz and above. Filtering this waveform with a 10-kHz filter will significantly reduce this error.

However, this does not work for the resolution of dc DAC values, i.e., that 47 thing we’ve been talking about. It is possible to produce a stream of values that, when averaged, will produce the desired value and a filter to remove the quantization error.

Suppose you have a DAC with 1-mV resolution and you would like to increase the resolution by a factor of eight to produce a value of 117.325 mV. This can be achieved by producing a cyclic data stream that is five parts 117 mV and three parts 118 mV.

The order in which the samples cycle depends on the type of dither used. For the three dither examples to follow, the desired result is 117.375 mV. This is 117 counts and a residue of 0.375.

This first example uses linear dither. Here a dither register is used to accumulate a value between 0 and less than 1. Because there are eight samples, the dither register is incremented by 0.125 for each sample. Its initial value is not important. (In this case we’ll use 0.043.)

Whenever the value exceeds 1, it rolls around through 0. For each cycle, a comparison is made to see if the sum of the residue and dither equals or exceeds one. If so, the nominal DAC value is incremented for that sample.

Table 1 shows a cyclic linear dither that repeats itself every eight samples. This method is sometimes called pulse width dithering (PWD). With only a single rising edge time and falling edge, this dither type is guaranteed to have the lowest possible frequency (DAC clock/number of samples).

While the previous example produced an output stream with the lowest possible frequency, this example produces the highest possible output frequency for a given DAC clock. Here a dither register is used to accumulate a value between 0 and less than 1. Its initial value is not important either. (In this case we’ll use 0.082.)

The desired residue is added to the dither register. If the value exceeds 1, then the register rolls around through zero and the nominal DAC value is incremented for that sample.

Table 2 shows a cyclic linear dither that repeats itself every eight samples. This method is sometimes called delta-sigma dithering (DSD). There are three 118 values dispersed as evenly as possible between the five 117 values. With three rise times and fall times, this dither type is guaranteed to give the highest possible frequency (DAC clock * residue).

With a higher output frequency, DSD is going to be easier to filter. However, it has the disadvantage that each DAC channel requires its own dither accumulation register. PWD will be harder to filter but requires a single dither register for all DAC channels.

The third type of dithering allows a higher frequency dither than PWD yet only requires a single dither register for all DACs. This new method requires a random number linearly distributed between 0 and 1.

A comparison is made to see if the sum of the residue and this random dither equals or exceeds one. If so, the nominal DAC value is incremented for that sample. It intuitively makes sense that if you have a residue of 0.375, statistically the sum of the random dither and the dither will only exceed 1 in three out of eight times.

Table 3 shows a linear random dither. Whenever the sum of the dither and residue exceeds one, the DAC value is incremented for that single sample. Like the other methods, there three 118 values and five 117 values. There are two rise times and two fall times, making this method faster than PWD but slower than DSD.

It is not easy to generate truly random numbers. Digital cyclic redundancy hardware can easily generate pseudorandom values, though—hence the name, pseudorandom dithering (PRD).

Dither With Filters

One of the simplest digital filters is a low-pass single-pole infinite impulse response filter (IIR). It is easily implemented in software:

Output += (Input – Output)/a;

This filter averages one part of the input and (a-1) parts of the old output to generate a new output. As a result, the larger the value “a,” the slower filter’s response. The data in Table 4 has a step response of 16 for an IIR that averages one part of the input and three parts of the output to generate the next output for both floating point and integer math.

Examining the floating-point data shows that the output is asymptotically approaching the step input’s amplitude. It is called infinite impulse because the effect of that initial zero is never going to completely go away.

However, the integer data provides another picture. Without the residue, it isn’t possible for the output to get any closer than (a-1) from the desired asymptote. The solution is to add some dither. As before, there are three types of dither.

For PWD, the following will be used:

Output += (Dither +Input – Output)/a;

Dither = mod(++Dither, a);

For the example of “a” being four, the dither will be a cyclic stream of 0, 1, 2, and 3.

For DSD, the following will be used:

Temp = Dither + Input – Output;

Output += Temp/a;

Dither = mod(Temp, a);

For PRD, the following will be used:

Output += ( (a*Random())>>8 +Input – Output)/a;

Random() is a function that generates an 8-bit (pseudo) random value. For the example of “a” being four, the dither will be a random distribution of the values 0, 1, 2, and 3.

Table 5 includes the data collected for all three types of dither. As before, this filter averages one part of the input with three parts of the old output. The input is a step with amplitude of 16. All three dither methods allow the output to eventually equal the input. Figure 3 shows how each responds. Fig 3. All three types of dither, as with a single-pole IIR filter, will adjust the output to eventually equal the input

The delta-sigma dither is guaranteed to be the highest frequency. It has the smallest error when compared against the floating-point value. Its downside is that each filter has to have its own dither register.

The pulse width dither is guaranteed to have the lowest frequency but also the largest error. However, it requires only a single dither register for all the filters and its dither is the easiest to calculate.

The pseudorandom dither has a frequency and error between the other two. While it only requires a single dither register for all filters, its dither is more difficult to calculate.

Conclusion

As odd as it seems, there are times when adding noise and filtering to your system can improve overall performance. Three kinds of dithering allow you to customize for your systems specific performance requirements. 