This Idea For Design was originally published July 12, 1990.
Comparator hysteresis can extend the dynamic range of ac signal measurement by autoranging an rms-to-dc converter. A circuit can be built with a dynamic range of 80 dB or more, and can resolve input signals from 1 mV to 10 V with less than 1% total error (Fig. 1). The circuit also maintains high accuracy while measuring various input waveforms with different crest factors, including variable duty-cycle pulses. The autoranging method can be utilized in other signal-processing applications as well.
The AD736 rms-to-dc converter is a 1-V, full-scale device. Voltage comparator IC3 can increase the full-scale input range to 10 V automatically. When the rms-to-dc operating range is exceeded, the comparator's hysteresis switches in an attenuator at the rms-to-dc converter's input. Concurrently, it adds a gain stage to the circuit's output-buffer amplifier, maintaining a steady output voltage.
The comparator has two stable overlapping output stages. The lower hysteresis-transition point is set at 90 mV, while the upper point occurs at 1 V. This minimizes the situations in which a varying input waveform produces a confusing or unstable output state. The comparator's logic-high output is typically 4.8 V. Resistor-divider network R5 and R6 attenuate the output by a factor of 4.8, setting the noninverting input to 1 V. Similarly, the comparator's logic-low output is typically 0.44 V, setting the noninverting input to about 90 mV.
For input signals within the 100-mV to 1-V-rms operating range of IC1, the state of the switches is such that the rms-to-dc converter is driven directly from the input signal, and IC2 operates as a unity-gain follower buffering the output of IC1. When the inverting input to the comparator exceeds 1 V rms, its output goes low. The analog switches are active low, attenuator network R1 and R2, and the gain stage consisting of R3, R4, and Rg, are switched on.
R1 and R2 attenuate the input signal by a factor of 10. This means that inputs between 1 and 10 V now fall within the normal operating range of the rms-to-dc converter. The AD736's output is then amplified by 10 and the true rms value of the input signal is retained. When the output signal drops below 900 mV rms, the output of IC1 falls below 90 mV, coming within the typical range of the rms-to-dc converter again. Then, the comparator's output goes high, the input attenuator is bypassed, and the output-buffer amp functions as a voltage follower.
Due to the circuit's attenuation, the frequency response for 2 V acts similar to that of 200 mV, and 10 V acts like 1 V (Fig. 2). This helps to improve the frequency response of large input signals. The low frequency cutoff (−3 dB) is 20 Hz. With the capacitor values shown, the rms converter's settling time is 360 ms for a 1-V symmetrical sine-wave input; the settling time is greater for input signals of decreasing amplitude. Settling time improves to 36 ms when CAV = 15 µF and CF = 1 µF. The low-frequency cutoff rises 200 Hz.
All measurements shown in the figure are for sine-wave inputs, and all voltage specifications are peak values. The circuit is calibrated using a sine-wave input greater than 1 V rms. The relationship between peak and rms value is given by:
The rms value of an untrimmed sine wave = VPEAK / √2.
Update by Barrie Gilbert and Dana Whitlow
In the original 1990 Idea For Design, gain switching was used to extend the dynamic range of ac signal measurement by providing autoranging for an rms-to-dc converter. When the operating range of the AD736 was exceeded, a comparator with hysteresis was used to switch in an attenuator at the input of the rms-to-dc converter and apply a compensating gain to its output.
With high-frequency rms detectors, extending the dynamic range is even more critical. This is because the currently available dynamic range is only about 30 dB at best for such detectors. Generally, this is insufficient for handling the combination of high crest factor and wide measurement range of complex high-frequency waveforms, such as the digital communications signals commonly employed today.
The simple circuit employed in 1990 can't be implemented now because the comparator delays and switching transients are too slow to handle broadband signals. But, the availability of accurate, high-frequency, variable-gain amplifiers (VGAs) and high-speed rms detectors allows alternative approaches. These enable users to avoid making step changes in gain. Through this updated circuit, a novel means for wide-range, true-rms measurement of complicated high frequency waveforms is presented (see the figure).
In this scheme, a VGA inserted into the signal path ahead of the rms detector becomes part of an AGC loop. It maintains the output of the rms detector at a constant value when the difference relative to a set-point is integrated to form a control voltage. That voltage is applied to the VGA, whose gain is an accurate exponential function of the control voltage, resulting in the control voltage being logarithmically related to the input. A prototype circuit conformed to the desired logarithmic response law within 1 dB over an 80-dB range of input-signal amplitude.
The high-frequency rms detector, AD8361, is burdened only with the crest factor of the signal waveform, because AGC action maintains its rms input at a fixed level. The loop's error integrator is differential, with one input driven by the output of the rms detector, and the other driven by a reference voltage that sets the detector output.
Both halves of a dual VGA, called AD605, are used in cascade. This provides a measurement range of 80 dB, even for a signal with a high crest factor, such as random noise. Each VGA is set for a slope of 20 dB/V by 2.5 V applied to its VREF pin, resulting in a maximum-control range of 40 dB per stage as the control voltage varies from 0.5 to 2.5 V. The maximum-gain range of IC1a is −14 to 34 dB with a jumper between its OUT and FB pins. The gain range of IC1b is 0 to 48 dB, by the absence of this jumper. Only the central 40-dB portion of each VGA's full-gain range is used.
Noise makes a growing contribution to the measurement as the VGA's gain increases in response to smaller input-signal levels. A three-pole low-pass filter is included in the signal path to prevent the rms detector from responding to broadband noise outside the desired passband. In this example, that's a few kHz to about 2 MHz.
The filter is split into two sections. The first section, IC2a, is located between the VGAs. It provides an active complex pole pair. Following IC1b, the second section, containing RFP and CFP, furnishes the third pole. For IF applications, a bandpass filter would be more appropriate. A passive filter would be suitable too. The cascade of two VGAs performs well up to about 10 MHz. As it has a higher gain, IC1b primarily limits the bandwidth. The AD8361 is essentially flat until around 1 GHz and has useful response to about 2.5 GHz. Therefore, measurements at higher frequencies will become possible as faster VGAs become available. These, however, will also need to provide a "linear-in-dB" gain function.
Though not obvious from examining the schematic, it should be noted that an attenuation of about 6 dB is inherent in the passive portion of the low-pass filter. This is due to the rms detector's 225-Ω input impedance working against RFP. In addition to the differing gain ranges chosen for the two VGAs, this ensures that the signal swings throughout the signal path remain within the linear limits of the active devices. When making changes, one must pay close attention to the distribution of gains and losses through the signal path.
The averaging time constant of the detector over which the "mean" is measured is set by CFIL, which is on pin 6 of IC3. The constant should be long enough to suppress ripple resulting from modulation on the signal. But, this filter adds a pole to the AGC loop which must be accounted for when choosing the integration time constant provided by IC2b and surrounding components. This is in order to ensure loop stability. Additional low-pass filtering of the output is supplied by RFIL2 and CFIL2 at the circuit's output. With the values shown, the overall measurement time constant is about 3 ms, and there's about 1 dB p-p of equivalent ripple on the circuit's output when the input signal is wideband random noise (flat from near dc to 2 MHz).
Located on pin 7 of IC3, RPD sinks current from the error integrator's summing junction when the output of the VGA cascade is below loop equilibrium. This drives the integrator's output more positive to increase gain. When the VGA's output is too high, the AD8361 output sources current to the summing junction. That drives the integrator's output lower, which results in reduced gain.
This circuit was designed for 5-V single-supply polarity operation. That guided the choice of the particular VGA (AD605) and op amp (AD8032) used for the circuit. The 2.5-V reference input to the AD605 needs to be stable and predictable because the output slope expressed in voltage per dB is proportional to that reference.