Electronic Design

Flexible, Modular Process Packs More Than Half A Billion Transistors On A Tiny Silicon Chip

A new ASIC process promises to address the density, speed, power, and cost issues of future communications applications. Known as Gflx, this flexible technology was tailored for versatility and modularity. Its developer, LSI Logic Corp., Milpitas, Calif., claims the process has catapulted the company a generation ahead of its competitors.

This development comes on the heels of an ever-increasing demand for greater Internet bandwidth. Designers of broadband infrastructure equipment and wireless handsets were forced to respond to this need. They had to integrate more functions and intellectual property (IP) on a single chip while satisfying different applications, each with an individual set of requirements. For example, in some designs, speed and bandwidth are favored over power consumption. In others, low power is considered the topmost priority. Then, there are a few that need to strike a balance between speed and power consumption.

As time-to-market is becoming crucial, implementing these myriad solutions and ensuring they work the first time is a matter of life and death for chip providers. Taking this into account, ASIC vendors like LSI Logic are developing robust processes. These processes are flexible and modular to meet the varying needs of mixed-signal designers developing system-on-a-chip (SoC) solutions for communications applications.

The Gflx process delivers totally new classes of communications solutions on a single chip, claims LSI Logic. Twice as dense as the company's previous-generation G12 process, Gflx is designed for 0.1-µm effective channel lengths (0.13 µm drawn) to offer 78 million usable logic gates. That's equivalent to 612 million transistors on a 20- by 20-mm silicon die.

Flexibility is afforded by allowing designers a choice between bandwidth and power-consumption levels. For instance, a wideband operating frequency of 650 MHz is possible with a power consumption of 9.0 nW/gate/MHz. With power-sensitive applications, the Gflx process can also be used to design ASICs that operate at 350 MHz, but consume just 8.0 nW/gate/MHz. By comparison, the 0.18-µm G12 process consumes 23.0 nW/gate/MHz.

LSI's latest Gflx process also provides eight layers of metal interconnections with seven options. To reduce RC-interconnect delays, the top two metal layers can be thicker and wider. A low-k (down to 2.8) interlayer dielectric is used for faster performance.

In addition, the process offers eight different modules to address a variety of user requirements. These include 1.5- and 1.2-V core libraries, mixed-signal functions, and high-performance and low-power transistors (see the figure). The 1.5-V library focuses on high-speed, high-performance designs and the 1.2-V library furnishes low-power building blocks. Application-optimized I/O sets, metal options ranging from four to eight layers, embedded SRAM, and embedded SRAM-based FPGAs are incorporated as well. For FPGAs, it provides up to 50k gates per block.

"This flexible process allows the designer to add or remove modules, depending on the application," states Ronnie Vasishta, LSI Logic's senior director of ASIC technology marketing. The mixed-signal module implements true 3.3-V mixed-signal transistors, metal-insulator-metal (MIM) capacitors, and a variety of passive-resistor types to permit optimal size, accuracy, and matching of transistors.

"It also enables cost-effective integration onto the digital part of the CMOS process," adds Vasishta. While the FPGA enables rapid reconfigurability of SoC designs, the memory comes with a broad range of compilers for optimizing embedded-memory functions.

Gflx prototypes will be available early next year, with production slated for late 2001. The Gflx process will be manufactured in the vendor's advanced foundries in Gresham, Ore., and Tskuba, Japan.

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