Numerous applications require the synthesis of a slightly offset frequency with respect to a given reference. The idea presented here uses a circuit to generate a 9.997925-MHz signal utilizing a 10-MHz reference. The frequency offset is low (only 2 kHz), which creates tight constraints on the design of mixers and filters.
The circuit employs a phase-locked-loop-based setup (Fig. 1). Figure 2 depicts a detailed schematic design of the proposed circuit.
In the frequency domain, the phase transfer function is:
where Φi(S) and Φo(S) are the Laplace transforms of the input and output phases and F(S) is the frequency response of the loops.
Output frequency stabilization time will depend on the loop filter characteristics. If the RC loop filter in Figure 2 is used, the phase transfer function will have the following expression:
When the steady state is reached (S = 0), the input-output frequency relation is equal to:
where SΦo(S) is the output frequency fo (or output phase derivative), and SΦi(S) is the input frequency (fi) in the Laplace-transformed domain. In the proposed design, the input frequency is multiplied by a factor: mp/n/q.
To generate the required offset frequency from the input reference, adequate m,n,p, and q must be selected. For the current application, the following values were chosen: m = 4819, n = 2410, q = 2, and p = 10.
Instead of using a 10-MHz oscillator, a circuit based on a 100-MHz VCO following a frequency divider was implemented. The reason for this selection is that higher frequency stability values can be achieved with this setup (a frequency divider at the output of a VCO). This configuration also achieves larger phase noise reductions. Another important feature is that TTL-compatible outputs are available for interfacing to general-purpose digital circuits. Furthermore, the oscillator is isolated from the circuit load by a prescaler or frequency divider. The phase comparator used is the MC145151-2, which produces the VCO control voltage signal at the output of the loop filter.
The VCO is tuned to approximately 100 MHz with a small range of variation. The generated frequency is divided by 10 using an SP8680B prescaler. Two signals are introduced to the MC145151-2 comparator, namely a 10-MHz reference clock and the PLL loop frequency. Both input signals go through two programmable counters. The reference frequency is divided by 2410 and the loop frequency is divided by 4819.
Figure 2 shows the implemented VCO based on a Colpitts configuration. Its output frequency can be controlled by a voltage level applied to a BB105 variable capacitor. The oscillator uses a 2N2222, the most commonly used transistor at frequencies between 50 and 100 MHz. All elements in the circuit are powered by means of a 5-V supply.