Electronic Design

High Integration Simplifies Signal Processing For CCDs

CMOS ICs Offer Complete Analog Signal Processing For CCD Imaging To Lower Overall Cost, Power Consumption, And Size.

The charge-coupled device (CCD) is the image sensor of choice for most consumer-oriented imaging applications. Traditionally, the device's unique analog signal-processing chain has been implemented using standard linear components—op-amps, analog-to-digital and digital-to-analog converters (ADCs and DACs, respectively), analog multipliers, and analog switches. Recent advances in semiconductor design and technology have allowed a number of companies to introduce a single integrated circuit (IC) to handle all of the signal-processing steps required, from the CCD output right through the analog-to-digital conversion. The devices retain the performance of traditional designs, yet provide substantial savings in cost, power, and size. Before taking full advantage of these devices however, it is important to fully understand what they can and cannot do.

The markets for scanners, digital still cameras (DSC), and camcorders have become extremely competitive. In all three, prices are falling as the imaging companies compete for market share. Typically, consumers demand that each new generation of products offer higher performance for the same price as previous models, or at least give comparable performance at a lower cost. With cameras in particular, smaller size and longer battery life are key selling points.

For semiconductor manufacturers, this means that the 8-bit ADC that was adequate for low-end scanners in the past, is now being replaced by a 10-bit converter. With camcorder and DSC applications moving to higher-resolution CCD arrays with higher pixel rates, these same manufacturers must produce the analog processing circuitry required to operate at the higher sampling rates needed to maintain proper readout times and frame rates.

Semiconductor companies are now offering integrated solutions for CCD signal processing that combine all of the necessary front-end analog circuitry. Although this yields an obvious reduction in size and potential cost savings, high integration alone will not help designers meet all of the consumer's requirements. To help the designer more effectively address all of their needs, these devices are being implemented using low-cost, low-power, standard CMOS processes. This approach is possible because semiconductor companies have improved their capabilities in CMOS analog circuitry, eliminating the need for proven, but costlier BiCMOS and bipolar implementations. The remaining challenge for the semiconductor companies is to achieve the performance level required for the different imaging applications.

Processing The Signal
To understand what the integrated signal processing components have to offer, consider the typical CCD output waveform (Fig. 1). One period of this signal consists of a reset feedthrough level, a reference level, and a data level. The voltage difference between the reference and the data levels contains the light information for an individual pixel. To accurately process and digitize the CCD signal, the integrated signal processing components perform several basic operations. These are: correlated double sampling (CDS), dc restoration (clamping), gain, offset, and analog-to-digital conversion.

CDS is one of the most important steps in processing the CCD waveform. The operation serves two important purposes: it calculates the difference between the reference and data levels of the CCD signal, and it reduces some of the noise components in the CCD signal. Conceptually, the CDS is a differential-in-time amplifier, because it takes two separate samples of the input signal and outputs the difference between them (Fig. 2). There are varied topologies being used to perform this operation.

By taking two samples of the CCD signal and subtracting them, any noise source that is correlated between the two samples will be removed. Furthermore, a noise source that is not correlated, but is slowly varying between the two samples, will be reduced in magnitude. Noise introduced in the output stage of the CCD shown in Figure 1 consists primarily of kT/C noise from the charge-sensing node, and 1/f and white noise from the output amplifier. The kT/C noise from the reset switch's ON-resistance is sampled on the sense node, where it remains until the next pixel. It will be present during both the reference and data levels, so it is correlated within one pixel period, and will be removed by the CDS. The CDS will also attenuate the 1/f noise from the output amplifier because the frequency response of the CDS falls off with decreasing frequency. Low-frequency noise introduced prior to the CDS from power supplies and by temperature drifts will also be attenuated by the CDS.

A typical CCD signal has a dc offset of anywhere from 3 to 9 V or more. Dc offsets of this magnitude are generally incompatible with CMOS signal-processing ICs. In most scanner and high-end camera systems, the signal processors use 5-V supplies, while in camcorders and digital cameras the signal processors use supplies as low as 2.7 V. An on-chip input clamp accomplishes the necessary dc level shift, and only requires the addition of an external coupling capacitor.

The CCD's dark current causes a difference between the reference and data levels of the CCD signal, typically ranging from 10 to 80 mV. If left uncorrected, this offset will reduce system dynamic range, particularly after gain is applied. The signal-processing component applies analog offset adjustment to correct the average level of the offset, thereby retaining the dynamic range. With the majority of the offset removed in the analog domain, the digital image-processing circuitry can perform fine offset adjustment on a pixel-by-pixel basis to correct for dark-current variations.

A programmable-gain amplifier is needed to match the CCD signal's maximum amplitude with the full-scale voltage of the ADC. Different CCDs for scanner and digital camera applications can have peak amplitudes ranging from 100 mV up to 3 or 4 V. Most CMOS ADCs have full-scale voltage spans of 1 to 5 V. If the CCD signal only spans 25% of the ADC's full-scale range, then two bits of dynamic range will be lost. A gain stage will amplify the CCD signal to the appropriate amplitude and use the ADC's full dynamic range.

Lastly, the ADC converts the conditioned analog signal into a digital representation, to be externally processed by application-specific digital circuitry. The speed and resolution of the ADC is based on the pixel rate and resolution of the application. A CCD with a maximum dynamic range of 55 to 60 dB would require at least a 10-bit ADC, while one with a dynamic range of 65 to 70 dB would require at least a 12-bit ADC. Additional resolution may be needed to allow headroom for the digital image processing. For example, 6 dB of digital gain reduces the dynamic range of the ADC by one bit, because only half of the ADC's input voltage range can be used.

Product Variations
There are two general types of analog front-end (AFE) products available—those targeted for scanner applications and those targeted for digital camera and camcorder applications. For the scanner market, devices are available with resolutions ranging from 8 to 12 bits, and sampling rates of 1 to 4 MHz per color. Features include the processing steps listed earlier. In addition, some devices may offer shading correction, which changes the gain at the pixel rate to correct lens attenuation across a scanned line; digital offset, which changes the offset at the pixel rate to correct for odd/even offset errors and fixed-pattern offset variations; programmable threshold detectors, for scanning black-and-white only documents; and programmable timing generators, which allow the user to program the linear CCD timing signals and the CDS sampling clocks. Other operating modes are sometimes included which allow the parts to process the outputs of contact image sensors (CISs) in addition to CCDs.

Scanners use color linear sensors, which have three CCD outputs representing the red, green, and blue information. Depending on the CCD used, the amplitudes of each color will be different due to differences in the spectral responsivity of each color. A separate programmable-gain-amplifier (PGA) stage will be needed for each color, so that the amplitudes may be individually adjusted to match the ADC's input range.

AFE products intended for digital camera and camcorder applications offer 8- to 10-bit resolution, and emphasize lower power (with 3-V supplies) and higher sampling rates (>10 MHz). A single-channel architecture is sufficient to interface with the output of an area-array CCD. The input ranges are smaller than the scanner products, to accommodate the lower output voltages of area CCDs. The programmable gain ranges are larger in order to be compatible with the wide range of lighting conditions in which a camera will be used (a scanner operates under more-controlled lighting conditions). The offset correction is implemented with an on-chip closed-looped configuration to correct the average offset of each line from the CCD in real time. This is different than the linear CCD approach, in which the individual pixel offsets are calibrated. This is not practical in most camera designs because of the memory and processing overhead that would be required to correct the entire area array.

Design Considerations
While it may seem like integrated CCD signal processors eliminate much of the system design effort, there are still some important decisions to make before choosing a device for a specific application. For example, these devices don't suit all imaging applications. Currently, 12 bits is the limit for the integrated products. Many high-end CCD applications require 14 or even 16 bits of resolution. These applications must still rely on discrete implementations. Many of the products cannot directly accommodate two other types of imaging sensors, such as CISs and CMOS imagers. These imaging sensors, while not currently up to the performance level of the CCD, potentially offer a lower system cost, and are now being used in some lower-end applications. A designer may wish to consider using an AFE, which can be used directly with CIS or CMOS sensors, to allow a future design path for lower-cost products.

When comparing different AFE products for a specific application, consider the minimum required features. The number of possible devices will usually be narrowed down based on whether the application is a scanner or a camera. Further consideration should then be given to the required sampling rate, the programmable gain range, the amount of available offset correction, and the ease of which the device can be interfaced with the rest of the system. Examine the characteristics of the analog inputs. Is there an input clamp to facilitate capacitor coupling to the external CCD buffer amplifier, and is the input range compatible with the CCD signal? Check the timing requirements for compatibility with the system timing generator. If the device requires a digital interface to program the gain and offset levels, be sure that it will be compatible with the system ASIC. Power-supply requirements also should be considered.

Of equal or greater importance to the above factors is the AFE's level of performance. Careful attention should be given to the performance specifications in the data sheet and the operating conditions under which they are tested. Integrated devices have different configurations and system settings, so it is important to understand how the device has been characterized by the manufacturer. Noise and linearity are two areas of particular interest in imaging applications.

Noise in the AFE consists of wideband noise from all of the analog circuitry and the ADC, and quantization noise from the ADC. Standalone ADCs usually specify a signal-to-noise (SNR) or signal-to-noise plus distortion ratio, but these types of measurements are not entirely useful in imaging applications. The converter SNR is tested with a sinewave input, and includes the effects of analog distortion, distortion and spurs from integral and differential nonlinearity (INL and DNL, respectively), quantization noise, and thermal noise. Sometimes multiple data records are averaged, reducing the contribution of thermal noise. The distortion numbers are not of interest in imaging applications because CCD signals are not sinusoidal in nature, and the front end of the ADC samples the CCD signal only during a relatively slow-moving portion of the waveform. Instead of using a traditional converter SNR measurement, consider the contribution from wideband noise, quantization noise, and DNL errors. If the noise specifications given for a particular AFE are unclear or nonexistent, the wideband AFE noise can be measured using a "grounded-input histogram test." Here, the inputs to the device are grounded, and a histogram is taken of the output data. The standard deviation of the histogram will give the RMS noise level of the device, not including the ADC quantization noise. A low-noise AFE can have a thermal noise level comparable to or less than the RMS quantization noise of its on-board ADC.

AFE noise is important because it can impact the system dynamic range. Dynamic range is determined by comparing the maximum signal that can be processed to the minimum signal level that can be resolved in the system. Noise from the CCD, from the analog signal processing, and from the ADC will contribute to overall system noise level. Assuming that the CDS will reduce the kT/C and 1/f noise contribution, the CCD random noise can usually be found from the CCD manufacturer—specified as "noise floor" or "random noise" in millivolts or electrons RMS. Note that wideband noise introduced by the CCD and additional amplifier stages will not be reduced by the CDS. If the input signal to the CDS is not band-limited to the Nyquist frequency, which it typically is not, to achieve the necessary settling accuracy, then wideband noise will be aliased. Though a complete analysis on the subject is beyond the scope of this article, there is an important trade-off involved in setting the analog signal bandwidth—too much and the noise may be unacceptable; not enough and the settling time may be unacceptable.

CCD fixed-pattern noise due to variations in the dark current of each pixel can be very objectionable in images, and should be included in the noise calculation if it is not reduced through calibration techniques. Noise also will be introduced by the external CCD buffer amplifier, though this can be minimized. The noise contribution from the AFE can be found on the product's data sheet, or measured using the grounded input histogram test. The ADC's resolution will determine the quantization noise level, which is calculated by dividing the weight of one LSB by ?—12. Adding all the noise sources in a root-sum-of-squares fashion gives:

This equation can be used in approximating the achievable dynamic range, to see if the AFE being considered is a good match for the CCD. Be sure to refer all noise sources to the same point in the signal chain when making the total noise calculation. To refer all noise sources to the ADC output, the CCD noise sources should be multiplied by the gain of the processing stages, and the AFE noise specification should be output-referred. Alternatively, all noise sources can be referred back to the CCD output, by dividing the ADC quantization noise and AFE output noise by the front-end gain. Understanding which noise sources are dominant will help in the selection of an appropriate AFE.

The AFE's linearity will also affect system performance. The nonlinearities of a real ADC can cause artifacts in the digitized image. DNL is very important, because the human visual system is good at detecting edges or discontinuities in an image. DNL is the variation in code width for the ADC. Poor DNL causes uneven gradations or "steps" in adjacent luminosity levels. A true 10-bit system demands DNL of better than 1 LSB at the 10-bit level, with 0.5 LSB preferable to avoid degradation of image quality. Products with DNL poor enough to cause missing codes can cause image artifacts in the digital processing and should be avoided. INL is also important but less demanding than DNL in terms of LSB size. The human visual system is less adept at distinguishing gradual nonlinearity which is spread out over the entire grey-scale range. However, large INL can contribute to errors in the color processing algorithms of a particular system, resulting in color-related artifacts in the image.

After selecting a possible AFE for the application, thoroughly evaluate the device to explore its true performance under specific operating conditions. Unlike the use of discrete components, the integrated approach does not allow the evaluation of each separate processing stage. Many manufacturers provide evaluation boards for their products to simplify this step of the design.

Application Example
An example of the Analog Devices' AD9807 used in a scanner design is shown in Figure 3. The CCD outputs are buffered with emitter followers or op amps to drive the signals from the CCD board through a flat cable to the main board. There the signals are capacitor coupled into the AD9807's analog inputs, and dc restored by the on-chip clamp circuits. The AD9807 processes and digitizes the signals to 12-bits. The digital outputs are then sent to the system ASIC where the digital image processing is performed. The timing signals are generated by the ASIC. Grounding, decoupling, and layout are critical, as with any high-speed application. In this circuit, a common ground plane is used under the AD9807. If a separate analog and digital ground is used on the main board, the grounds should not be split under the AFE, to prevent digital noise from coupling through the IC into the analog signal path. Instead, the entire AFE should be placed on the analog ground plane.

Future Integration
Additional integration seems logical to continue the low-cost, highly integrated strategy. Now that good analog performance is possible with standard CMOS processes, it should be possible to integrate some or all of the back-end digital processing of the imaging system. As the level of complexity goes up, power and ground management on the chip is critical to minimize digital noise coupling into the analog circuitry. Inclusion of such features as a SCSI interface on-chip is particularly challenging, due to the large driver currents required.

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