Electronic Design

Integration To Dominate Power-Conversion Design

Clustering functions in mixed-signal integration is a blossoming trend in several categories—commercial-off-the-shelf (COTS) devices, application- and customer-specific ASICs, and multichip (MCM) package integration. That's good news for power-conversion engineers jockeying for market share with designs that promise to reduce cost, component count, and space. After last year's downside, 2003 promises to be a year of significant integration. Emerging architectures and topologies can potentially enable much higher levels of integration in power-conversion designs.

Ironically, mixed-signal technology is getting a big boost from the purely digital side of the tracks as more designs include analog IP. This will nurture the mixed-signal technology much more than the lower volume demand from the analog side. Now at 0.45 µm, what will be the next cost-optimized feature size for mixed-signal? At a lower feature size, IP creation activity is expected to reduce function cost. On the flip side, packaged COTS and ASIC device cost probably won't decrease as more functions are added to a particular device's portfolio.

For power supplies, emerging architectures offer paths to the two- to five-chip designs. Two topologies/architectures, digital control and secondary-side control, might offer paths to significantly lower chip count. For ac-dc power supplies, we can expect a large number of off-line ICs and power ICs for 120-VAC applications and some for 240-VAC off-line designs. For ASIC houses, the voltage ceiling was 80 V until recently. Look for 100-V and higher ASIC technologies to be offered this year.

BiCMOS will continue to be preferred for crafting power ICs. COTS devices and ASIC designs will adopt more high-density, low-power portable electronics IPs.

Are COTS suppliers taking the ASIC approach? Some traditional standard device suppliers are using the ASIC IP approach to provide faster time-to-market for combinational regulator devices (ICs that include one or two synchronous buck regulators and three to four LDOs). Quick design-in demand could drive more of this process adoption by standard IC suppliers.

On another front, both IC and discrete power semiconductor designers will offer unique alternatives to "functional" power ICs. The "startups" have an excellent opportunity here as the traditional suppliers work hard to meld technology adaptations into their less-than-flexible streamlined production lines.

The traditional power IC boundaries of integration will move very little during the year. This is due to two cost sacrifices. The first of these is the large silicon sacrifice posed by lateral BCDMOS MOSFETs. The other sacrifice is the large number of masks required (15 to 18) for 20% of the chip area. BCDMOS continues to be used for MCM power ICs in the low-ampere range. MCM power ICs provide the lowest-cost solution for the higher currents.

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