Electronic Design

Interface High-Performance Op Amps With ADCs

Give your system a boost by interfacing high-end op amps with ADCs, using one of three different driver architectures.

The source that drives high-resolution analog-to-digital converters (ADCs) sees a high-frequency ac load and a dc load of a few hundred ohms or more. Thus, a high-performance op amp with high input impedance of a few megohms and low output impedance would be an ideal choice as an input ADC driver. The ADC driver acts as a buffer and a low-pass filter to reduce overall system noise.

As signals travel through the traces of a printed-circuit board (PCB) and long cables, system noise accumulates in the signals and a differential ADC rejects any signal noise that appears as a common-mode voltage. Using differential signals rather than single-ended signals has a couple of advantages: Differential signals double the dynamic range of the ADC, and they offer better harmonic distortion performance.

There are several ways to produce differential signals from a dual-op-amp configuration. Two popular methods are single-ended-to-differential conversion and differential- to-differential conversion. The former method requires a single input source, while the latter requires a differential input source. To utilize the full dynamic range of the ADC, the input must be driven to full-scale input voltage.

This article discusses three different ADC driver architectures: single-to-single, single-ended-to-differential and differential-to-differential. It provides, in a concise manner, all of the necessary information for interfacing high-performance op amps with ADCs.

Several key elements must coalesce for effective analog front-end design in the signal path (Fig. 1). The typical signal path’s analog front-end includes an op amp that drives the ADC, an RC filter, and the microcontroller or digital signal processor (DSP).

A real-world input source can have non-ideal impedance. Thus, a buffer amplifier, with very low output impedance, is required to drive the input of the ADC. The external RL-CL filter works as an anti-aliasing filter that helps lower the noise bandwidth of the ADC driver and buffer the charging transients caused by the ADC sample-and-hold circuit. To minimize the droop in the input voltage, external shunt capacitance (CL) should be about 10 times larger than the internal input capacitance of the ADC. In addition, external series resistance (RL) should be large enough to maintain the phase delay at the output of the op amp and hence maintain the stability.

Most applications benefit from the inclusion of a series isolation resistor connected between the op-amp output and ADC input. This series resistor helps limit the output current of the op amp. The value chosen for this series resistor is very important, since a higher value will increase the load impedance seen by the op amp and improve the op amp’s total-harmonic-distortion (THD) performance. However, the ADC prefers to be driven by a low impedance source. Thus, the optimum value for this series resistor must be found so that it will offer the best performance in terms of THD, signal-to-noise ratio (SNR), and spurious free dynamic range (SFDR) of the combined op amp and ADC.

When interfacing an ADC with an op amp, it’s imperative to understand the specifications that are important to get the expected performance results. Modern ADC ac specifications such as THD, SNR, settling time, and SFDR are critical for filtering, test and measurement, video, and reconstruction applications. The high-performance op amp’s settling time, THD, and noise performance must be better than that of the ADC it’s driving to maintain the proper system accuracy with minimal or no error.

For this article, either the LMH6611 or the LMH6618 single op amp is used to drive the single-channel ADC121S101 ADC, and either the LMH6612 or the LMH6619 dual op amp drives the differential input ADC121S625 or ADC121S705 ADC. These amplifiers are designed for ease of use in a wide range of applications requiring high speed, low supply current, low noise, and the ability to drive complex ADC and video loads.

Some system applications require low THD, low SFDR, and wide dynamic range. Others require high SNR, potentially sacrificing THD and SFDR to focus on noise performance.

Noise is a very important specification for both the op amp and the ADC. Three main sources of noise contribute to the overall performance of the ADC—quantization noise, noise generated by the ADC itself (particularly at higher frequencies), and the noise generated by the application circuit. The impedance of the input source affects the noise performance of the op amp. Theoretically, an ADC’s SNR can be found from the equation:

SNR (in dB) = 6.02N + 1.72

where N is the resolution of the ADC. For example, according to this equation, a 12-bit ADC has an SNR of 74 dB. However, the practical SNR number would be about 72 dB. To achieve better SNR, the ADC driver noise should be as small as possible. The LMH6611/LMH6612/LMH6618/LMH6619 have low voltage noise of only 10 nV/vHz.

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The combined settling time of the op amp and the ADC must be within 1 LSB. The 0.01% settling time of the LMH6618/LMH6619 and of the LMH6611/LMH6612 are 120 ns and 100 ns, respectively.

The ADC driver’s THD should be inherently lower than that of the ADC. The LMH6618/LMH6619 have an SFDR of 100dBc at 2-V p-p output and 100-kHz input frequency. The LMH6611/LMH6612 have an SFDR of 90 dBc at 2-V p-p output and 1-MHz input frequency.

Signal-to-noise and distortion (SINAD) is a parameter that combines the SNR and THD specifications. SINAD is defined as the RMS value of the output signal to the RMS value of all the other spectral components below half the clock frequency, including harmonics but excluding dc, and can be calculated from SNR and THD according to the equation:


Because SINAD compares all undesired frequency components with the input frequency, it’s an overall measure of an ADC’s dynamic performance.

The single-to-single ADC driver architecture has a single-ended input source connected to the input of the op amp. The single-ended output of the op amp is then fed to the single-ended input of the ADC. The low noise of only 10 nV/\\[SQ RT HZ\\] and a wide bandwidth of 130 MHz make the LMH6618 an excellent choice for driving the 12-bit, 500-ksample/s to 1-Msample/s ADC121S101 ADC, which has a successive approximation architecture with internal sample-and-hold circuits.

Figure 2 shows the schematic of the LMH6618 in a second-order multiple feedback with gain of -1 (inverting) configuration, driving an ADC121S101. The inverting configuration is preferred over the non-inverting configuration as it offers more linear output response. Table 1 shows the performance data of the LMH6611 or the LMH6618 combined with the ADC121S101.

The FFT plot of the LMH6611 and ADC121S101 combination (Fig. 3) was tested at f = 200-kHz input frequency. The ADC driver’s cutoff frequency of 500 kHz is found from the equation:


The op amp’s gain is set by the equation:


The single-ended-to-differential ADC driver utilizes an LMH6619 dual op amp to buffer a single-ended source to drive an ADC with differential inputs (Fig. 4). One of the op amps is configured as a unity-gain buffer that drives the inverting (IN-) input of op amp U2 and non-inverting (IN+) input of the ADC121S625.

U2 inverts the input signal and drives the inverting input of the ADC121S625. U2 is configured for a gain of +2 to reduce the noise without sacrificing THD performance. The common-mode voltage of 2.5 V is set up at the non-inverting inputs of op amps U1 and U2. This configuration produces differential ±2.5-V p-p output signals when the single-ended input signal of 0 to VREF is ac-coupled into the noninverting inputs of op amps U1 and U2. This configuration produces differential ±2.5-V p-p output signals when the single-ended input signal of 0 to VREF is ac-coupled into the non-inverting terminal of the op amp, and each non-inverting terminal of the op amp is biased at the mid-scale of 2.5 V.

The two output RC anti-aliasing filters are used between both the outputs of U1 and U2 and the input of the ADC121S625 to minimize the effect of undesired high-frequency noise coming from the input source. Each RC filter has a cutoff frequency of approximately 22 MHz. Figure 5 shows the FFT plot of the LMH6619 and ADC121S625 combination tested at f = 20-kHz input frequency. Table 2 provides performance data for the LMH6612 with the ADC121S625 and the LMH6619 with the ADC121S625.

The LMH6619 dual op amp can be configured as a differential-to-differential ADC driver to buffer a differential source to a differential input ADC (Fig. 6). The differential-to-differential ADC driver is formed using two single-to-single ADC drivers. Each output from these drivers goes to a separate input of the differential ADC. Here, each single-to-single ADC driver uses the same components and is configured for a gain of -1 (inverting).

Table 3 summarizes the performance of the LMH6612 combined with both the ADC121S625/ADC121S705 and then the LMH6619 combined with both ADCs. It includes data for both op amps, the LMH6612 and the LMH6619, interfaced with both ADCs (each at two different frequencies). To utilize the full dynamic range of the ADC, the maximum input of 2.5 V p-p is applied to the ADC input. An FFT plot shows the LMH6612 and ADC121S625 combination tested at f = 20-kHz input frequency (Fig. 7).

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Connecting the input source ground with the supply ground is a critical factor in layout. For each ADC driver configuration, it’s important to account for the impedance of the signal source when setting up the resistor networks to ensure that the differential outputs have the same gain. For example, an audio precision signal generator has about 22 O of source impedance and the board has a 50-O termination. Therefore, the designer must adjust the proper gain and input to obtain the desired signal at the output of the op amp.

The following are recommendations for the design of PCB layout in order to obtain the optimum high frequency performance:

• Place the ADC and amplifier as close together as possible.
• Put the supply bypassing capacitors as close as possible to the device (<1 in.).
• Utilize surface-mount instead of through-hole components and ground and power planes.
• Keep the traces short where possible.
• Use terminated transmission lines for long traces.

The PCB layout of the differential-to-differential configuration is shown in Figure 8.

In summary, considerations such as the selection of the external RL-CL network are of paramount importance. Also, the op amp’s critical parameters—THD, settling time, and noise—must be taken in to account to interface a high-performance op amp with an ADC. By employing one of three different ADC driver architectures, and paying careful attention to grounding and PCB layout, system performance can dramatically improve.

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