Electronic Design

ISSCC>2002: Analog, Online

Other session 13 highlights include a presentation by Maxim Integrated Products, which introduces a fifth-order multibit delta-sigma (Δ-Σ) analog-to-digital converter (ADC) with 14-bit resolution and a 4-MHz conversion bandwidth (Paper 13.4). For higher integration and reduced costs, it's implemented in 0.18-µm CMOS. It uses a data-weighted averaging (DWA) algorithm in the feedback loop to improve the spurious-free dynamic range (SFDR) by about 20 dB. The ADC achieves an SFDR of 103 dB at a low oversampling ratio of 8 (see the figure).

To minimize component sensitivity, modulators in this design are based on low-Q biquad circuits. Because this topology also exhibits low sensitivity to finite op-amp dc gain, it facilitates operation at a supply voltage of as low as 1.8 V, where it consumes about 149 mW, with the analog portion accounting for 102 mW. This work was conducted in collaboration with the Department of Electrical & Computer Engineering of Oregon State University, Corvallis.

The drive to push ADCs closer to the RF front end of a highly digitized Universal Mobile Telecommunication System (UMTS) receiver has prompted developers at Philips Research Laboratories to craft a fourth-order continuous-time Δ-Σ modulator with a 1.5-bit quantizer and a feedback digital-to-analog converter (Paper 13.5).

This design has a 70-dB dynamic range with a bandwidth of 2 MHz . It employs a three-level quantizer to reduce quantization noise and sensitivity to clock jitter, while obtaining good linearity without using dynamic element-matching techniques. The sampling rate is 153.6 MHz for an oversampling ratio of 40. This chip, which has two modulators, a PLL, an oscillator, and a bandgap reference, dissipates 11.5 mW at 1.8 V. It's implemented in 0.18-µm CMOS.

In another accomplishment, researchers at Infineon Technologies, in cooperation with the Technical University of Munich, Germany, successfully lowered the supply voltage for a voiceband Δ-Σ ADC to 0.7 V (Paper 18.3). A second-order switched-op amp Δ-Σ modulator with MOSFET capacitors for linearization is used. The MOSFET capacitors enable the ADC to maintain compatibility with a fully digital mainstream CMOS process. Because it employs different common-mode voltages for the op amp's inputs and outputs, this design doesn't require low-Vt devices or bootstrapping.

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