LVPECL/LVDS Clock Distribution Chips Conquer Metastability
Metastability, which essentially means chaotic output behavior resulting from input glitches, can be a source of system failures in clock distribution. Input glitches are inevitable in hot-swap applications. Micrels latest LVPECL/LVDS
Metastability, which essentially means chaotic output behavior resulting from
input glitches, can be a source of system failures in clock distribution. Input
glitches are inevitable in hot-swap applications. Micrel’s latest LVPECL/LVDS
fanout buffers, though, prevent unwanted oscillations and maintain output stability
when an input signal’s swing collapses or disappears.
The “Fail-Safe Input” (FSI) family includes the SY89467U (LVPECL)
and SY89468U (LVDS) 2:1 multiplexer-input buffers with a fanout of 20. They
join existing 1:2 and 1:8-fanout LVPECL and LVDS products. Each device offers
a three-pin internal termination architecture that can interface to any differential
signal (ac- or dc-coupled) as small as 100 mV (200 mV p-p) without the need
for level shifting or termination resistor networks in the signal path.
The SY89467U outputs are 800-mV LVPECL with rise/fall times guaranteed to be
less than 110 ps. For the SY89468U, outputs are LVDS-compatible with the same
timing specs. Jitter performance is guaranteed to be less than 10 ps p-p over
temperature and voltage.
