Electronic Design

New Approaches Speed Up Optimization Of Analog Designs

As more ICs incorporate some analog functionality, the demand for analog CMOS design will greatly increase. Not only will the number of new designs increase, but so will the number of legacy designs that must be ported every eight to 12 months to the newest process. In both cases, time-to-market is critical. This comes during a great shortage of experienced analog designers. Predictions abound that analog design will become a critical bottleneck for next-generation system-on-a-chip (SoC) designs.

In the traditional "Spice and tweak" method, the analog designer cycles between modifying a design and simulating. This puts a premium on the analog designer's very scarce time. Although sizing a circuit to meet specifications can be challenging and interesting, it can become drudgery. The traditional method requires a great deal of analog design experience, a reasonable starting design, and sometimes just luck. It won't be able to keep pace with the coming demand for analog circuit design.

Several efforts are under way to develop computer-aided analog design and synthesis methods to meet the rising challenge. While many have been developed, none is widely accepted. One group is based on automating the Spice and tweak cycle, replacing the analog designer with an optimization engine, such as simulated annealing. This is slow, needs a reasonable starting design, and requires an experienced analog designer to babysit to ensure that the optimization routine isn't jammed, to select a new topology, and so on. For many designers working under tight schedules, a "reasonable starting design" is good enough, so "Spice and tweak" is an unnecessary luxury.

Another "equation-based" group of methods formulate the design problem using simple equations to describe device models and constraints. These can be fast, as the equations are easier to evaluate than a whole Spice run. But they suffer from low accuracy, so the designs still require much hand-tweaking after the optimization process.

Intuition suggests a natural tradeoff between simplified, highly approximate models (simple equations), resulting in easy to solve optimization problems, and sophisticated, accurate models (Spice), resulting in very difficult optimization problems. In the first case, one gets fast results that might not be accurate. Accurate results are achieved with the other, but the optimization phase is very slow and requires much babysitting. Either way, a lot of analog design time and effort is required.

The accuracy versus speed tradeoff can be beat, however. New interior-point methods for solving special types of nonlinear optimization problems can be used to design analog and RF cells, like op amps, comparators, or CMOS inductors, in seconds. These methods not only achieve accuracy, but they also can easily handle the much larger problems that arise when synthesizing much larger blocks, like PLLs or switched-capacitor filters.

For each analog cell, up to thousands of equations are formulated, each with many nonlinear terms, to capture design constraints and relate design variables to the specifications. This step relies on new, proprietary device models and a number of internal tools developed for this task. The large set of complex design equations achieve an accuracy similar to Spice. They can still be solved rapidly and globally, though, because of their very special form. An analog cell can be synthesized directly from user specifications, without any initial design, in a fraction of the time that it takes to verify the design in Spice.

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