Electronic Design

Peer Through The High-Performance Kaleidoscope

Every twist of the wrist reveals a new vista in analog design.

Surveying the “high-performance” analog landscape is a lot like looking through a kaleidoscope. With each turn, you’ll see performance characteristics: precision, bandwidth, conversion rates, noise, power consumption, physical size, dynamic range, price, etc. Depending on the application, you may be happy to sacrifice some to optimize others.

Turn the kaleidoscope a little, and you’ll see basic topologies or input/output configurations. Turn again. Analog-todigital converter (ADC) “performance” characteristics overlap depending on whether they’re pipelines, successive approximation registers (SARs), folded-interpolated, or delta-sigmas. Lately, thanks to National Semiconductor, it also depends on whether the delta-sigmas have the old-fashioned discrete-time inputs or whether they’re continuous-time delta-sigmas.

Yet some of this view also depends on characteristics such as reference voltage and clock stability, what kinds of clever tricks designers use to split the input signal between multiple data converters, the voltage range of the input signal, and whether it’s double-ended or ground-referenced. What it boils down to is that one engineer’s high-performance needs differ from those of another engineer at a company down the road.

Then let’s have some folks in marketing shake the kaleidoscope. Some will tell you that they’re getting beat up by customers who simply can’t duplicate the chip company’s datasheet guaranteed performance specs on their production boards. Another group thinks its applications engineers should create bulletproof reference designs for its front-end amps and data converters.

Others think it’s best to customize the silicon totally so that analog comes in one end and data comes out the other, while still others take a modular route, with multiple die in a single package. Indeed, it’s not unheard of to find combinations of these approaches in a single company, depending on the sales volumes of the potential enduses of the products.

With another turn of the kaleidoscope, one can look at analog performance in terms of the absolute physical limits of thermal noise or clock jitter. Is there some kind of absolute Heisenberg limit you can’t beat? This is where the question of high performance gets really interesting.

I talked to a number of people in preparing this article, and I confess the most stimulating conversations occurred in the lab at Linear Technology, where I got to pull the legendary Jim Williams away from his test bench and engage him on the topic of high performance.

When the discussion turned to fundamental physical limitations, Williams surprised me by insisting that no one—not Boltzmann, not Shannon, but no one—had the power to say “Thus far, and no further.” He thought it wasn’t so much a matter of cheating. Rather, it involved renogotiating the physical issues that we engineers have to face and overcome.

He presented me with a number of examples, most of which I should have seen coming. The chopper-stabilized amplifier and the sigma-delta modulator, he pointed out, were two examples from long, long ago that overcame “fundamental physical limitations” by redefining the problems.

More recently, Williams said, Intel had at least temporarily put the gate leakage problem aside and gained several more generations for Moore’s law by resurrecting the multicore processor approach attempted by Sun with SPARC in 1992. It didn’t work for Scott McNealy, but had for Paul Otellini.

Curiously, since we were talking about parallel processing, Williams’ real hero on the digital side is Gene Amdahl, which surprised me. Williams started talking about oscilloscope probes, which seemed to be a change in topic. But at least I was on firm ground since I’d spent several years working at Tektronix and figured I knew a 465 from a 7912. He then described how an oscilloscope probe and vertical amplifier “broke the rules” about transmission lines.

Essentially, the probe doesn’t cause a significant perturbation on the point in the circuit it’s measuring. Also, the probe reactance is adjusted to “compensate” for transmission- line effects. Therefore, what the vertical amplifier presents to the scope display circuitry is an accurate representation of what’s going on down at the probe tip.

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Anyone who used a scope probe in Beaverton in the 1970s was sure to get a lesson in how to find the square-wave reference signal on the scope and in how to tweak that compensation screw on the probe. So, I understood Williams’ point about “breaking” the rules.

What I didn’t know was that Amdahl had understood that concept to the point where he used it on the backplanes of his minicomputers—a “renegotiation” of the laws of physics that saved Amdahl all sorts of interconnect headaches. IBM did something similar with disc drives.

National Semiconductor got considerable attention early in 2008 for bringing to market the first continuous-time deltasigma ADC, the 12-bit, 50-Msample/s ADC12EU050 (Fig. 1). Unlike a discretetime delta-sigma, a continuous-time converter moves the sampling operation from the input to the ADC to just after the forward loop filter in the modulator. But what’s so good about moving the sampling operation downstream?

In a discrete-time delta-sigma ADC, there is, as in most ADCs, a switched-capacitor filter. Designing one requires the creation of fast settling circuits and an input buffer to eliminate sample glitches. Also, switched-capacitor input filters set their poles and zeroes through capacitor ratios relative to the sampling clock frequency. Because capacitor thermal noise is inversely proportional to capacitance, the capacitors must be relatively large to obtain the best signal-to-noise ratio (SNR).

In addition, to acquire an accurate representation of the input signal on a hold capacitor, the input stages must settle to a finite level dictated by the accuracy limits of the system. During acquisition, settling time depends on the exponential time constant and slew rate of the system.

What’s good about discrete-time ADCs is that their input filter characteristics scale with clock frequency. Filter performance, therefore, always matches the sample clock rate. On the other hand, the higher the clock frequency, the more dynamic power is consumed.

In a continuous-time design, the filter characteristic depends on conventional active-filter design rules. If the sample rate is changed to match input-signal bandwidth, the continuous-time filter must be retuned. It becomes a real challenge to ensure that a single product platform can support a wide range of sample rates. A further challenge lies in achieving high linearity in high-resolution implementations, because the loop filter requires lots of gain.

Continuous-time design was so difficult, it essentially remained a laboratory curiosity for decades. But in 2005, Xignal, a fabless German company, made some breakthroughs. Then National bought Xignal and successfully transferred the laboratory technology to a production technology, which is no mean feat.

Some of the ADC12EU050’s special features take advantage of the oversampling architecture. One example is the chip’s integrated low-pass, brick-wall antialiasing filter. That means no external antialiasing filter is needed. The continuoustime architecture also means the IC has an easy-to-drive, purely resistive input stage that, of course, doesn’t require a sample-andhold amplifier.

National overcame the continuous- time architecture’s traditional susceptibility to clock jitter with an integrated phaselocked loop (PLL) and voltagecontrolled oscillator (VCO) for clock conditioning. The converters provide on-chip instantoverload recovery circuitry that recovers from saturation within one clock cycle if the input exceeds pre-determined limits.

Okay, let’s say you need to design a battery- powered instrument for measuring temperature, pressure, or some other sensor- related characteristic, or maybe even voltage, at a reasonably slow rate, say, up to 60 times a second. For battery-operated applications, Linear Technology and its 16-bit (guaranteed no missing codes) delta- sigma LTC2451 and LTC2452 ADCs offer a small footprint (3- by 2-mm dual flat no-lead package) and low (0.5-µA) shutdown current.

These devices operate from a single 2.7- to 5.5-V supply. They even have a built-in oscillator. The difference between them is that the LTC2451 communicates via I2C and can measure a single-ended input between 0 V and VCC, while the LTC2452 communicates via the serial peripheral interface (SPI) and can measure a differential input up to ±VCC.

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Changing converter topologies, the company’s LTC2366, a 12-bit, 3-Msample/s SAR ADC, emphasizes a small (TSOT-23) footprint and low power draw (7.2 mW at 2.6 to 3.6 V). It’s part of a five-member family that aims to give designers of portable medical devices and the like a way to trade off performance for price.

All of the devices in the family communicate via a serial SPI/QSPI/Microwire-compatible interface and offer no data latency while achieving dc specifications of ±1-LSB integral nonlinearity (INL) and differential nonlinearity (DNL). The LTC2366 measures 72-dB SNR, –80-dB total harmonic distortion (THD), and 82-dB spurious free dynamic range (SFDR) at a 1-MHz input frequency.

One way to position analog parts with respect to performance is to focus on applications. For instance, EMI can be a headache in certain apps. An injected RF signal in a weigh scale can result in as much as 1 V of output offset, which would diminish a 10-bit ADC’s resolution (1024 codes) to a 3-bit effective number of bits (ENOB).

For use in precision weigh scales, as well as phone accessories, medical instruments, and other EMI-sensitive industrial electronic equipment, National recently introduced the LMV831 single, LMV832 dual, and LMV834 quad op amps. All of them integrate EMI filters that deliver a 120-dB EMI rejection ratio (EMIRR).

Obviously, not every designer may be familiar with that spec. To help explain it, National provides app note AN-1698 (www.national.com/an/AN/AN-1698.pdf ) and evaluation boards along with complete signal-path solutions based on the LMV83x devices and 10- and 12-bit ADCs with 1-LSB performance SPI or I2C interfaces.

Another instrumentation amp with RF filtering on the input comes from Texas Instruments. The company notes that “special filters have been integrated in series with the inputs of the INA333 to reduce RF interference” that can cause offset voltage variations in weigh scales (Fig. 2). TI goes on to explain that it focused its design efforts in the INA333 on combining “long battery life, low noise, and low offset voltage and drift.”

The chip utilizes a special zero-drift technology, which incorporates a proprietary switched-capacitor notch filter to eliminate chopping noise and provide very low input voltage noise of 50 nV/Hz. Specifically, the amplifier is spec’d for 75-µA quiescent current at 1.8 V. Offset is 25 µV with an offset drift of 0.1 µV/°C. Input bias current is 200 pA.

Looking at 16- and 18-bit precision instrumentation applications like radar-based collision avoidance and medical instrumentation, Analog Devices came up with the low-noise ADA4898 op amp, which combines low distortion, low noise, and high speed. ADI acknowledges that it’s essentially a companion part for the company’s AD7631 and AD7634 precision data converters.

The ADA4898 uses the same commonmode linearized input ADI first used in the AD8099, a circuit designed for low noise. In the case of the new op amp, that means ultra-low broadband noise (less than 1 nV/Hz), 1/f noise of 1.2 nV/Hz at 10 Hz, low distortion (–110 dBc at 500 kHz), and dc precision that optimizes 16- and 18-bit ADC performance. At unity gain, the 3-dB bandwidth is 70 MHz, and the slew rate is 40 V/µs.

For MRI and digital X-ray systems, key goals are to reduce the time that patients must lie motionless during MRI examinations and reduce X-ray radiation exposure. With that in mind, Analog Devices engineers developed the 16-bit, 10-Msample/s AD7626 successive-approximation ADC. It achieves a 15-bit ENOB thanks to its 92-dB SNR, which is 8 dB better than any ADC, regardless of architecture. The AD7626 additionally wins points on size (5- by 5-mm quad flat no-lead) and power consumption (13 mW).

For driving high-performance 14- and 16-bit converters in communications infrastructure and high-speed instrumentation equipment, ADI focused on low distortion in developing its silicon-germanium (SiGe) ADA4939 differential amplifier, which consumes less than 120 mW from a single 3.3-V supply. In terms of distortion, it achieves 82-dB SFDR at 70 MHz. The new amp is available in one- and (for I/Q demodulation) two-channel versions.

The two-channel version also limits crosstalk to –80 dB at 100 MHz, while providing gain and phase matching. The amplifiers can be used in either differential-to-differential or single-ended-to-differential configurations.

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An internal common-mode feedback loop allows the user to independently adjust the output common-mode level to match the input common-mode voltage of the ADC as well as achieve exceptional output balance and suppression of even-order harmonics. Other key specs include its 2.3-nV/Hz input voltage noise, 1.4-GHz, –3-dB bandwidth (G=+2), and 5000-V/µs slew rate.

For quadrature demodulation schemes, Linear recently announced dual versions of its LTC6400/LTC6401 differential driver. The dual LTC6420-20 and LTC6421-20 add guaranteed ±0.25-dB gain matching and typical ±0.1° phase matching to the noise and distortion performance of the original singles. Channel separation is 80 dB at 100 MHz. The LTC6420-20 provides a fixed gain of 20 dB with –84-dBc thirdorder intermodulation distortion (IMD3) at 100-MHz input frequency. Input voltage noise is 2.2 nV/Hz, including internal gain-setting resistors.

These amplifiers achieve their distortion and noise specs on a single 3-V supply and have rail-to-rail (R-R) output swing. Thus, the dual ADCs and amplifiers are able to share the same voltage supply in many applications. These drivers can drive an ADC directly without any external output impedance matching and convert single-ended inputs into differential outputs. The LTC6420-20 operates from dc to 300 MHz. The lower-power/lower-priced LTC6421-20 operates to 140 MHz.

In the August 14 issue, I wrote about Maxim’s MAX2065 fully programmable analog and digital IF/RF variable-gain amplifier, which is a nice example of advanced design (see “RF/IF VGA Chip Does It All,", ED Online 19427). Maxim packed a linearly controlled, 31-dB voltage-variable attenuator; a 31-dB digital step-attenuator; a 22-dB gain driver amplifier; an 8-bit, control digital-to-analog converter (DAC); and a simple SPI-compatible interface into one chip.

The point was to come up with a virtual Swiss Army knife for applications in GSM/EDGE, CDMA, WCDMA, LTE, and WiMAX receivers. Designers can use the MAX2065 as either an IF or RF allpurpose variable gain amplifier (VGA), interfacing directly with 50- systems operating anywhere between 50 and 1000 MHz. Each of the three independent RF stages has its own RF input and RF output, so the chip can be configured to optimize either noise figure or linearity (Fig. 3).

Another approach to “high performance” is to take an intransigent problem that’s been bugging circuit designers for decades and solve it for them. That’s what Texas Instruments did this year with some of its R-R op amps. The first was the OPA365 in January, and the latest was the OPA369 in June. The latter does it with less power.

The basic problem is that the input stage for most R-R amps consists of a p- and n-channel differential pair in which offset voltage depends on the common-mode input voltage. In other words, there’s a nonlinearity as the input signal passes through the crossover point between the two devices, and that limits the amplifier’s total harmonic distortion (Fig. 4). To combat the problem, TI’s chip designers use a charge pump that boosts the positive supply by about 2 V to supply the input tail current for a pMOS differential pair on the input.

In the OPA369, this approach delivers an offset voltage of 750 µV over the entire R-R input range and a common-mode rejection ratio (CMRR) of 100 dB minimum, maximizing the usable input dynamic range for low-supply-voltage applications. Other features include an input voltage noise density of 120 nV/Hz, a 12-kHz gain-bandwidth, an input bias current of 50 pA maximum, a voltage offset drift of 1.75 µV/°C (max), a power-supply rejection ratio (PSRR) of 94 dB, and 1/f noise of 3.6 µV p-p from 0.1 to 10 Hz.

The OPA369 offers the precision, low power, and small packaging required in a wide variety of applications. These range from portable medical devices (glucose meters, oxygen metering), portable instrumentation (gas detection/monitoring), and sensor signal conditioning to fitness-related portable consumer equipment, cellular phones, and handheld test equipment.

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