Electronic Design

"Ping-Pong" Configuration Increases System's Conversion Throughput

Traditionally, "ping-pong" configurations have been used with sample-and-hold circuits to increase throughput rates in data-acquisition systems. To increase throughput, this same technique can be implemented with standard analog-to-digital converters (ADCs). With this arrangement, it's possible to double the throughput achievable with a single converter.

In this ping-pong circuit arrangement, the same analog source is connected to the analog inputs of both ADCs (Fig. 1). While one ADC is converting the analog input, data is being read from the other. By interleaving the conversions, the latency from the conversion time of the converter is removed. This leads to a 100% increase in the system throughput.

Each of the two AD7819s (an 8-bit parallel-output ADC) has output rates up to 200 kHz. Using the ping-pong technique outlined above, the system throughput rate can be increased to 400 kHz. Both ADCs complete a conversion in 5 µS, creating the overall conversion rate of 400 kHz.

Control and synchronization of the system are managed by the —-CONVST and BUSY lines of the ADCs. The input clock determines the data-output rate from the system. —-CONVST signals are derived from a D-type flip-flop that divides the 400-kHz input clock input by a factor of two. This division then drives both ADCs at their maximum conversion rate. The 200-kHz outputs from the flip-flop, which are 180° out of phase, are applied to the —-CONVST pins of the ADCs. This ensures that one converter is in conversion mode, while the second is in read mode. The BUSY signals are used to control the multiplexing of the buses from the ADCs. These signals also are used to interrupt the controller, signifying that it's valid to read data from the bus.

Figure 2 demonstrates the timing and control for the ping-pong conversion circuit. A conversion is initiated on the falling edge of the —-CONVST signal. At the same time, the ADC's BUSY output will go high. Once the conversion is complete, the BUSY line returns low. The BUSY lines from the ADCs are AND-ed together to produce an output signal that indicates when a conversion has been completed on one of the ADCs. This signal interrupts the controller, informing it that a data result can be read from the data bus.

As indicated by the first falling edge of this signal, a conversion is completed on ADC #1. According to the second falling edge, a conversion is completed on ADC #2. This sequence is continually repeated. Another function of the AND-ed BUSY signals is to drive the clock input of a second D-type flip-flop. The output of this flip-flop forces the select pin of the multiplexer to select the proper ADC data output to apply to the bus.

The sequence to complete 1 byte being read from each ADC is as follows:

  1. Start conversion on ADC #1.
  2. Conversion completed on ADC #2. Multiplexer selects ADC #2 output. Interrupt processor. Read 1 byte from ADC #2.
  3. Start conversion on ADC #2.
  4. Conversion completed on ADC #1. Multiplexer selects ADC #1 output. Interrupt processor. Read 1 byte from ADC #1.
  5. Sequence repeats.

Figure 3 illustrates the performance levels for the ping-pong arrangement using the AD7819. What the plot shows is the result of a 4k FFT sampling at 400 kHz with a 125-kHz input signal. The signal-to-noise ratio (SNR) is 45 dB, which is quite acceptable for an 8-bit system. In order to achieve acceptable dynamic performance, it's important that the two ADCs be matched. If an offset error exists between the two converters, it will introduce a spur into the FFT. This, in turn, will degrade the system's performance.

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