Electronic Design

PMOS Transistor Guarantees Accurate Power-Up Sequencing

A TFT LCD panel requires three voltages: VDD, VON, and VOFF. VDD, typically 13 V, powers the video signal path. VON, usually 25 V, supplies the turn-on gate drive bias voltage for the TFT cell. Finally, VOFF is generally −10 V and provides the turn-off gate drive bias voltage for the TFT cell. Correct power-up sequencing between the three voltages is critical to prevent a false image from appearing on the monitor during startup.

Due to its high current requirement, VDD is generated by a boost converter and VON is created by a charge pump (Fig. 1). VDD and VOFF share the same enable control pin, so they are enabled together during power-up. The VON enable delay time is set by the 200-kΩ resistor and 0.1-µF capacitor powered from VIN. It's helpful to see the waveform of the charge pump output at the source of the PMOS FET (Fig. 2). The intermediate voltage step on the VCP waveform results from disabling the charge pump and pulling VCP to VDD levels through the D1 and D2 diodes.

The second large voltage step occurs after the charge pump is enabled. Powering the TFT LCD panel directly from VDD and VCP can prematurely charge on the TFT LCD cells, causing a false video signal on the monitor. A simple solution is to follow the VCP with a PMOS FET, as shown in the schematic in Figure 1. The gate of the PMOS is connected to VDD before the charge pump is enabled, when VCP is at the same potential as VDD. So, the PMOS does not have enough bias voltage to turn on. As a result, the VON output stays low. After the charge pump is enabled, the VCP voltage goes much higher than VDD. The PMOS is turned on and provides a current path to VON (Fig. 3).

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