Electronic Design

Remove Large Common-Mode Signals Using Standard Op Amps

In many industrial applications, signals requiring analog-to-digital conversion ride on a large I common-mode signal of up to a few hundred volts. A familiar problem in these applications is removing this common-mode signal. Doing so enables conveRSion using standard components operating from ±15-V or 5-V supplies.

This circuit uses a standard dual amplifier to remove a large common-mode signal from a 4-to 20-mA loop (Fig. 1). To convert the signal minus the common-mode to its digital 16-bit equivalent, this application uses the AD7707 sigma-delta (Σ-Δ) converter operating from a single 5-V supply.

RS is the sense resistor in the 4- to 20-mA loop. The signal generated across RS sits on a common-mode signal of 100 V. Removal of the commonmode voltage is accomplished by the first amplifier (A1). At its output, the second amplifier (A2) provides the differential voltage across the sense resistor RS.

The maximum signal at the output of A2 is 10 V. A2’s output drives the analog input (AIN3) of the AD7707. This, in turn, provides a full-scale range of 10 V when operating in the singlesupply (unipolar) mode. A negative supply is needed to subtract out the positive common-mode voltages. Therefore, A1 is required to be a dualsupply amplifier.

Here, the output of A1 sits at -10 V. Resistor pairs R5/R2 and R4/R3 need to be accurately matched to remove the common-mode signal. Similarly, the resistor ratio of the R1/R2 pair must be matched to the ratio of the R6/R5 pair. The trim resistor in series with R2 is used to remove mismatch errors. Once the maximum commonmode voltage is applied to the circuit, this trim resistor is used to calibrate the output of amplifier A2 to equal the voltage across RS. With A1 and A2 configured as in Figure 1, and with a fixed voltage applied across RS, the common-mode voltage (VCM) was varied from 0 to 100 V. The circuit’s common-mode rejection was typically 75 dB. Also, the error at AIN3 resulting from the change in common-mode voltage is measured.

The AD7707 analog-to-digital converter (ADC) used in this application is a Σ-Δ converter with on-chip digital filtering. This type of converter excels at measuring wide dynamic-range, low-frequency signals such as those in industrial-control or process-control applications. In addition to the Σ-Δ (or charge-balancing) ADC, this device also contains a calibration microcontroller with on-chip static RAM, a clock oscillator, a digital filter, and a bi-directional serial communications port.

Included within the AD7707 IC are two low-level pseudo-differential input channels and one high-level singleended input channel. This application uses the high-level input channel. Onchip thin-film resistors allow ±10-V, ±5-V, 0- to +10-V, and 0- to 5-V input signals to be directly accommodated on this analog input channel (AIN3) without requiring split supplies or charge-pumps.

The selected input signal is applied to a proprietary programmable-gain front end based around an analog modulator. An on-chip digital filter processes the modulator output. Using an on-chip control register, this digital filter’s first notch can be programmed to allow adjustment of the filter cutoff and the output update rate.

The AD7707 also contains a serial interface that can be configured for three-wire operation. Gain settings, signal polarity, and update rate selection can be configured in software using the input serial port. The AD7707 has self-calibration and system-calibration features that allow the user to eliminate gain and offset errors in the ADC itself or in the system. Operating at 3 V with a 1-MHz master clock, the AD7707 consumes less than 1 mW. This makes it ideal for use in lowpower systems. It also has a standby mode in which the current consumed is less than 8 µA.

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