Designs for rms converters are common, particularly the single-chip monolithic solutions. This circuit (see the figure), however, differs from the others because of its versatile instrumentation-amplifier-type differential inputs that feature excellent common-mode rejection (CMR). In addition, the circuit is built with inexpensive, generic components.

The first step in input-signal processing is the differential-input absolute-value
circuit (*ELECTRONIC DESIGN*, *April 16, 1992, p. 93)*. It consists
of A1, A2, Q1, Q2, and input-scaling resistor R_{1}. The zero-adjustment
trimmer pot provided for A1 permits accurate calibration for low-level inputs.
The absolute-value circuit displays a common-mode voltage range of ±10 V, a CMR equal to that of A1 and A2, and an input impedance of
≈10^{12}. It produces a current-mode output
at the collectors of Q1 and Q2 with a magnitude of V_{1}/R_{1}.

This current is applied to diode-connected Q3, which produces a voltage that's
logarithmically related to abs (V_{1}/R_{1}) as the first stage
of signal processing in the rms computing circuit. The rms computation is performed
by a variation of the so-called "implicit" method. The log signal
produced by Q3 is doubled by A3 and then applied to antilog transistor Q4. Because
antilog (2 log(x)) = X_{2}, the collector current of Q4 (I_{Q4})
is proportional to the instantaneous square of Q3's collector current. I is
averaged and converted to output voltage V_{0} by A4.

Amplifier A5 and transistor Q5 produce a signal related to log(V_{0}),
which is applied to the emitters of Q3 and Q5. This effectively subtracts it
from the V_{BE} of Q3 and adds it to the V_{BE} applied to Q4.
Due to the relationship of addition and subtraction of logarithms to multiplication
and division, the net result of this log(V_{0}) feedback is that I_{Q4}
is proportional to V_{1}^{2}/V_{0}. Because V_{0}
= avg(I_{Q4}R_{0}), V_{0} = avg(kV_{1}^{2}/V_{0}),
V_{0}^{2} = k avg(V_{1}^{2}), and V_{0}
= K rms (V_{1}). K and ak are appropriate constants.

The scale factor of the rms conversion, K, is given by (R_{FR}_{0})^{1/2}/R_{1}.
In the example circuit, the scale factor equals 10. Thus, a differential input
signal of 1 V_{rms} produces a V_{0} of 10 V.

Circuit frequency response includes both dc and those ac components with frequencies
both well above the R_{0}C_{avg} output time constant (<<
10 Hz in the example), and below the slew rate and gain-bandwidth limitations
of amplifiers A1 and A2 (>300 kHz for —3 dB in the example).

Within this range, circuit linearity is better than 1%. "Crest factor" capability is good due to the lack of voltage compliance limitations in the rms computation loop.