Toshiba will deploy Cadence's Virtuoso UltraSim Full-Chip Simulator among its analog and mixed-signal chip designers to conduct reliability analysis at 65 nanometers and below. The companies worked together to implement Toshiba's reliability models into Virtuoso UltraSim simulator using the UltraSim Reliability Interface. "With the Cadence Virtuoso UltraSim, Toshiba can provide highly reliable ICs for our customers, who provide consumer electronics applications, telecom-related products and peripheral devices," Masazumi Shiochi, group manager of the mixed signal CMOS design group at Toshiba's semiconductor company, said in a statement. The Virtuoso UltraSim is the Cadence FastSPICE circuit simulator used to verify large custom, analog mixed-signal, RF, memory, and SoC designs. It uses true hierarchical simulation to provide full-chip transistor level verification, regardless of design type or stage in the design cycle, according to a Cadence release.