Electronic Design

Universal Low-Jitter Level Shifter Drives High-Performance ADCs

This idea describes a circuit that converts a low-phase-noise sinusoidal signal into a low-jitter square wave, suitable to drive analog-to-digital converters (ADCs). The square wave's amplitude and average value are adjustable to comply with any desired logic level. The design also allows for differential, or single-ended, signaling.

As ADCs increase in speed and resolution, the quality of the ADC's clock becomes more and more important. For example, the ADC10D040 is a dual 10-bit, 40-MHz ADC with the excellent channel matching necessary for low-error-rate I/Q digital communications. But to see the highest level of performance, it needs an extremely low-jitter clock. Crystal oscillators are often employed because of their excellent jitter performance. But they're limited to the discrete set of frequencies offered by the manufacturer.

Another challenge is finding test equipment that features clock signals with very low jitter and an adjustable time base. The circuit shown in the figure was used to test the ADC10D040 over a wide range of conversion rates. However, it also is practical in system designs where clocks must be level-shifted, reshaped, and/or converted from single-ended to differential with a minimum of added jitter.

The circuit derives a low-jitter square wave using Agilent's 8644B sine-wave signal generator. The 8644B has a phase noise of −136 dBc/Hz, and a time-base resolution of 0.01 Hz, making it an excellent source for generating low-jitter clocks. The MC10EP05 is a high-speed differential ECL AND gate. With VCC set to 0 V and VEE set to −5 V, the part operates in NECL mode. In this mode, a logical "1" is −1145 mV ≤ VL ≤ −820 mV, and a logical "0" equals −1870 mV ≤ VL ≤ −1620 mV (at room temperature). The arithmetic mean of these extremes is 1345 mV. Because 1.2-V references like the LM4041-1.2 are readily available, it's used as the common-mode voltage.

The input sinusoid from the 8644B is ac coupled through C2, with R7 supplying a 50-Ω termination to 1.2 V. Capacitors C5 and C6 provide a low-impedance ac path to ground. U1 should be mounted close to R7 to minimize the trace length, and thereby lessen reflections. The amplitude of the sinusoid at the D1 input swings through both threshold points, toggling the matched bipolar pairs of U2. U1's differential outputs will swing between −945 mV ≤ V ≤ −1745 mV (typical). R8 and R9 terminate the ECL signal to −2 V, as required to operate the emitter outputs of U1.

A and B trace lengths may be increased as desired, so long as a 50-Ω characteristic impedance is maintained. R5, R6, R8, and R9 should be mounted close to U2, terminating the A and B transmission line.

R5 and R6 introduce a differential base current into U2's matched pair. L1, Q1, R11 to R14, and D2 form a temperature-stable current source. The expression for the current in terms of the circuit values is:

If R1 = R2 = R, the high and low voltages of the clock waveform are:

VHI = VPEAK     (2A)

VLO = VPEAK − (I × R)     (2B)

respectively. Equations 2A and 2B reveal that the amplitude and offset of the output voltage can be made adjustable by adapting I and VPEAK. This output provides a high degree of versatility: The output signals can be differential, or single ended, allowing for the generation of NECL-, PECL-, CMOS-, TTL-, and LVDS-compatible clock levels.

Another advantage of this circuit is that it doesn't disturb the ground plane much due to the "current-steering" topology. It's important to keep differential lines close together to contain the fields of the signals. R1 and R2 can be changed to match different transmission-line characteristics if desired.

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