Electronic Design

Use Hybrid PMOS-NMOS Active Loads To Cut Substrate Noise In Differential Amplifiers

BY MAKING A RELATIVELY simple change in a differential amplifier stage, designers can significantly reduce the sensitivity to digital switching noise. In mixed-signal ICs, digital switching noise couples through the common substrate into analog circuits, degrading their performance. In CMOS circuits, most substrate noise couples into NMOS transistors through backgate modulation. That is, the substrate acts as a second gate with a transconductance gain typically equal to about 20% of the normal gate transconductance gain.

PMOS transistors are less vulnerable to substrate noise since they’re placed in separate wells; designers implement guard rings to attenuate the substrate noise propagation. However, substrate noise can penetrate through guard rings and propagate inside isolated regions (Fig. 1).

The proposed change to the structure of a differential amplifier stage makes the circuit insensitive to substrate noise. In a typical differential amplifier, the active loads use four NMOS transistors, with M1 and M4 configured as diodeconnected and M2 and M3 as current sources. Substrate noise couples into these transistors, modulating the electrical impedance of the loads and thus the gain of the amplifier.

Replacing the diode-connected M1 and M4 NMOS transistors with source-follower PMOS transistors can solve this problem. The PMOS transistors are placed in an n-well and have the gates connected outside the n-well to the p-substrate through p+ contacts (Fig. 2a).

The output impedance of the M1 source-follower equals 1/gm1, which is the same as if M1 were configured as diode-connected by having the gate connected to VSS. Since M2 is configured as a current source and M1 has the same impedance as in a diode-connected configuration, the new active load functions similarly to the conventional active load.

M1’s gate senses the noise in the substrate and varies M1’s drain current. To achieve noise cancellation, this variation must be equal in magnitude and opposite in sign compared to the substrate noisegenerated drain current variation of M2. If so, the M1 and M2 current variations cancel each other, and the active load impedance doesn’t vary with substrate noise.

To determine how to achieve noise cancellation, calculate the impedance of the active load. The dynamic current through the active load can be calculated by connecting a test voltage, Vx, and calculating the resulting current, Ix (Fig. 2b). Then:

Ix = Vx(gm1 + gmb1) + Vsub(gmb2 – gm1)

where Ix is the current, Vx is the voltage drop on the load, Vsub is the substrate noise, gm is the main gate transconductance, and gmb is the backgate transconductance of M1 or M2.

If the PMOS and NMOS transistors are sized so that gm1 = gmb2, the Vsub term vanishes and Ix = Vx(gm1 + gmb1). In this case, the active load impedance ZLOAD = 1/ (gm1 + gmb1) and doesn’t depend on substrate noise.

To validate this technique, a differential amplifier with noise cancellation was implemented as a ring oscillator in a CMOS test chip together with a second ring oscillator built using conventional active loads.

With an injected sinusoidal substrate noise of 50 mV at 5 MHz, the output frequency spectrum of the ring oscillator without noise cancellation exhibited sidebands of 40 dBm amplitude at a 5-MHz frequency offset (Fig. 3a). The output frequency spectrum of the ring oscillator using active loads with noise cancellation had sidebands that were 22 dB lower (Fig. 3b).

Device mismatches between the NMOS and PMOS transistors can affect the suppression efficiency, but experimental results on multiple wafers showed that this effect wasn’t significant. Also, powersupply noise may couple into the n-well. However, biasing the n-well from a separate voltage generated with reference to ground can reduce this effect.

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