This article describes a design for a precision clock-generator circuit board that can function as a waveform generator in some telecom- or datacom-specific lab bench work. The clock generator outputs an array of clocks at fixed frequencies, and it accepts an external synchronization clock reference as an input.
At the core of the design is U1, a ZL30407 Sonet/SDH network element phase-locked loop (PLL) (Fig. 1). The ZL30407 will produce an array of Sonet and PDH clocks synchronized to a 20-MHz input master clock. When coupled with a Stratum 3 or higher-quality master clock, its outputs will meet Stratum 3E holdover accuracy requirements.
U1 may be configured with DIP switches to run in hardware mode. It's also possible to program small frequency offsets on the ZL30407 output clocks. To do this, the device must be operated in software mode. Software-mode operation requires an external controller to read and write the internal device registers via an 8-bit parallel port. For example, the device's microport interface may be adapted to interface with an IEEE 1284 PC printer port (U12), and a CPLD (U13) to implement the port-interface logic.
A 10-MHz sinusoid synchronization reference input of about 1 V p-p is converted to a CMOS square clock using a comparator (U2) and then doubled in frequency using a clock multiplier (U3). Multiple clock-generator boards may be synchronized to one another by connecting the Syncout of one board as the 20-MHz input to another. A ZL30406 PLL (U4) serves as a jitter filter to clean up the selected input clock. One additional clock buffer (U5) selects between a local TCXO (Y1) and external sync reference as the master board clock. To center the ZL30406 VCO on 20 MHz, an external resistor must be substituted with the one shown in the datasheet guideline.
The ZL30407 has 12 output clocks, five of which are shown in the example circuit. The CMOS outputs shown include 19.44 MHz, an 8-kHz frame pulse, 2.048 MHz, and 1.544 MHz. The depicted allocation of output clock pins to fan-out buffers (U7, U8, U9, and U10) and connectors has no particular constraints, other than appropriateness for the targeted application. Each clock is buffered to provide some fan-out and cable drive capability into the coax connectors.
A second ZL30406 (U6) converts one of the C19o output clocks into a very low-jitter differential CML output clock, selectable as one of four frequency multiples (19.44 MHz, 38.88 MHz, 77.76 MHz, and 155.52 MHz). U11 is a hardware-configurable differential clock frequency divider, which can be programmed using DIP switches to divide the ZL30407 chip's 155-MHz low-voltage differential signaling output clock down by 1, 2, 4, 8, or 16 in frequency.
Jitter measurements of each output clock were taken to verify the performance of the design. In summary, clock jitter was observed to be in line with datasheet specifications for the ZL30407 and ZL30406 devices. RMS jitter levels on the ZL30406 outputs ranged from 2 to 8 ps, and they compared favorably to the same measured at the output of a good function generator using a measurement bandwidth of 12 kHz to 20 MHz.
Figure 2 shows a phase-noise plot of the 155-MHz CML output clock for ZL30406 (U6). The ZL30406 PLL loop filter is configured with a bandwidth of 14-kHz.