Electronic Design

Watch That Layout

Noise and jitter that affect bit error rate (BER) on high-speed data buses is one thing. But electromagnetic interference (EMI) is another, more traditional noise problem. EMI has become a problem for power-supply designers, now that efficiency has popularized switched-mode supplies. Chip manufacturers now make more applications information available to engineers who design using their chips.

National Semiconductor provides layout recommendations specific to its LM3100 Simple Switcher synchronous 1-MHz, 1.5-A, step-down voltage regulators. Figures 1a and 1b show before and after scope shots from two boards that use the LM3100 and an identical set of components. Input is 12 V, and output is 3.3 V at 1.5 A.

The side-by-side sweeps in Figures 1a and 1b were made at 500- and 25-MHz bandwidths. But 1a has 100-mV/div vertical scale, while 1b has a 20-mV/div scale. The spikes in the before picture are nearly 300-mV p-p, even when the bandwidth is limited. In the after shot, even at 500 MHz, the spikes are only about 20 mV. With the bandwidth limited to 25 MHz, the spike amplitude is actually below the overall ripple envelope.

The difference is entirely in the layout. Figure 2 shows both sides of the before and after boards. The critical difference is the way the low-side switch and the input caps connect. On the before board, the chip’s power-ground pins connect to the output capacitor ground rather than the input cap grounds.

The input capacitor ground connections are located in the top left area of the board. As a result, the switch currents must return all the way around the board through a large array of vias and then via the very cut-up ground plane on the back side of the board. That large loop is the primary cause of all those output spikes. Also, the small-signal components for the feedback divider are spread out across the board.

On the after board, the input capacitors connect directly to the chip’s die-attach paddle. This keeps the high di/dt currents out of the main ground plane. The small signal components are positioned close to the IC with short traces connecting to the appropriate pins.

Because this is a two-layer board, a couple of traces had to be run through the ground plane on the back side of the board. In a way, though, that minimizes the disruption of any return currents that have to flow on through the plane. Top-side grounding was configured to virtually eliminate the need for ac currents to return through the plane in the first place. The result is a tight layout, that as the scope shots illustrate, is extremely quiet.

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