Electronic Design

What's All This Pease-Cohen Effect Stuff, Anyway?

Back in 1965, I designed one of the best op amps in the world, the PP25A. It had less than 1 mV of VOFFSET, and 150 pA of IBIAS, using good Amelco n-channel JFETs. Its yellow epoxy package had an impedance far above 1 million megohms. Nobody had a better amplifier. Then I designed an improved one, the PP25C, using TI JFETs. The input current was less than 15 pA in standard tests (at VCM = 0 V).

Then I applied these PP25Cs with our PPT&H Track-and-Hold Module. Our leak-rate tester said that the leak rate was good at 0 V of VCM, and at +10 V of VCM, but it degraded rapidly at a VCM of ­10 V. In fact, the input leakage there seemed to be worse than the standard PP25A!

We did some extended evaluation on these TI FETs. When we tested for IGSS, with no drain current flowing, the IG was quite small. But when we measured the IG as a function of IDS, the IG increased about linearly with the IDS. Oops! Further, this excessive gate current increased exponentially when the VGD passed a threshold! Bummer! And, this leakage increased even on the Amelco FETs, if we got the VDS big enough (see the figure).

Why was this happening? I cooked up a theory that it was related to the imperfect contact of the drain, to the drain's metal. When drain current flowed, much of the current flowed properly into the drain. But a portion of the current flowed back as minority carriers and was collected at the gate. This effect was magnified when the VGD got large. Joel Cohen of Crystalonics had observed this effect and had a similar theory. We mashed our theories into one and called it "The Pease-Cohen Effect (PCE)."

Soon, we found other data that debunked this theory. Apparently, this excess leakage is caused by "hot electrons." It can even occur in MOSFETs, flowing to the back gate (substrate). It is typically a bigger effect in p-channels than n-channels and bigger in compact, high-performance, tiny-geometry FETs. But, it was NOT caused by imperfect metallic contact at the drain. So we had to throw that theory out. Yet when engineers bump into this, we still say, "Oh yeah, that's the Pease-Cohen Effect."

So if you discover that a JFET's gate leakage increases dramatically, linearly with the drain current, at high voltages, don't be surprised. If some FETs work well, don't let anybody swap in an "equivalent" type, with no proper qualifying tests. The "equivalent" may have completely different (worse) amounts of PCE leakage.

Comments invited!
[email protected] —or:
Mail Stop D2597A, National Semiconductor
P.O. Box 58090, Santa Clara, CA 95052-8090

P.S. One day, Amelco's salesman, Ed Barrett, came by with a "new, improved" matched JFET pair, but he wouldn't let me evaluate it. He said, "Everybody wants to evaluate this FET by putting it on the curve-tracer. Some customers think it's the best matched pair they ever saw. Others look very closely, and they say it's not all that well matched." I asked Ed why he wouldn't let me evaluate it. He said, "It wouldn't work well for you because you would plug it into the front end of an op amp—and it would not work." He admitted, "That is because it is really just one FET inside, bonded out to both sides of the six-pin package. It looks pretty good on a curve-tracer. But if you tried to use it, it wouldn't amplify." A point well taken! The joke was on—everybody else!! /rap

P.P.S. Could I have starved down the PP25C's source currents from 300 to 50µA and run the amplifier with lighter damping? That would have decreased the excess gate current by 6×. But I never thought of that until just now! Dumb! /rap

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.