TSMC Helps LSI Reduce Leakage By 25% On Next Generation Product

Jan. 27, 2010
TSMC Helps LSI Reduce Leakage By 25% On Next Generation Product

Amsterdam, The Netherlands: The Taiwan Semiconductor Manufacturing Company (TSMC) has announced that the LSI Corporation achieved over 25% overall leakage reduction in a next generation product by implementing TSMC's PowerTrim power-optimization technology on the company's 65nm low-power (LP) process.

PowerTrim is a technology that blends a layer of design technology with semiconductor processing to optimize a design's power leakage. Tela Innovations provides the patented PowerTrim technology and services under an exclusive license to TSMC.

PowerTrim software analyzed the LSI design and substituted cells with small increases in gate length on non-critical timing paths. These small changes make a significant impact since increasing gate length exponentially reduces leakage current.

PowerTrim performs speed/power tradeoffs using a CD biasing technique that analyses designs and applies gate length biases to the appropriate cells (i.e. non-critical paths possessing sufficient timing "slack"). The technology optimizes transistors along these paths without reducing chip performance. The gate CD biases are implemented as part of the Optical Proximity Correction (OPC) flow. The process does not impact cell footprint or chip area. The result is significant leakage power reduction while maintaining chip performance and area. PowerTrim also reduces leakage power variability resulting in improved parametric yield.

The PowerTrim service is implemented in conjunction with other leakage reduction techniques such as multi-Vt cell libraries, reverse body biasing, header/footer sleep switches, and voltage islands. It provides additional leakage improvements and is more efficient in terms of leakage reduction per unit of slack than high-Vt transistors.

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