International Research Project Targets Advanced SiP Technologies

Electronics companies and research institutions from nine different EU countries will take part in the largest European project to research and develop highly integrated electronic system-in-package (SiP) solutions. Work on the ESiP project (Efficient Silicon Multi-Chip System-in-Package Integration) will focus on developing reliable and more easily testable technology for the design and manufacture of complex microelectronics. The project, led by German chip company Infineon Technologies, is scheduled to operate until April 2013.

System-in-package technology is the positioning of different chips, either next to each other or stacked up on each other, in a single package. SiP technology for applications in sophisticated electronic products is considered a particularly strong growth area in the electronics sector. Its technical advantages are well known, such as smaller size, reduced profile, and lighter weight. Particularly important are the improved noise characteristics and faster processing times.

Future developments could involve different chips integrating various production processes and architectures into a standard chip package. Potential examples include a special 45nm processor, a high-frequency 90nm communications chip, and sensors and passive components such as miniaturized capacitors or filters.

One major objective of the European ESiP collaboration is to investigate the reliability of new production processes and materials required to create SiP systems. The project will also look into new methods for error analysis and testing. It’s expected that the results of the ESiP project will find applications in electric vehicles, medical equipment, and communications technology.

Industry experts consider SiP technologies to be a base concept for future electronics systems that make complete technical solutions possible. One such example would be the ability to produce a micro camera in a SiP package. This would involve stacking different types of chips (3D integration), combining them intelligently, and integrating them in a functional chip package.

Infineon's contribution to the project is to develop system integration solutions comprising several microchips and improve them in terms of failure analysis, reliability, and testability.

The total budget for ESiP is around €35 million, with 50% of the total being financed over three years by the 40 project partners. Two-thirds of the other half will be provided by national funding organizations in Austria, Belgium, Finland, France, Germany, Great Britain, Italy, the Netherlands, and Norway, and a third by the European Union (European Nanoelectronics Initiative Advisory Council ENIAC and the European Regional Development Fund).

In addition to the Free State of Saxony in Germany, the German Ministry of Education and Research (BMBF) is also sponsoring the ESiP project as part of the government’s high-tech strategy and Information and Communications Technology 2020 program (IKT 2020), with funding of around €3.1 million. The BMBF is the biggest sponsor of the participating European state authorities.

Hide comments


  • Allowed HTML tags: <em> <strong> <blockquote> <br> <p>

Plain text

  • No HTML tags allowed.
  • Web page addresses and e-mail addresses turn into links automatically.
  • Lines and paragraphs break automatically.