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ARM offers adaptive verification IP for on-chip communication

At the 44thDesign Automation Conference, ARM introduced AMBA adaptive verification IP, technology for verifying on-chip communication systems by extracting and applying traffic profile information to predict how systems will perform.

Jonathan Morris, general manager of ARM’s System Design Division, said adaptive verification IP “combines the time-to-market advantages of automated verification with the quality of in-context, knowledge-based verification that was previously only possible manually.” He added that the technology “complements existing random or directed-random methods with a new approach to reducing overall verification time, improving verification confidence, and enabling the explosion in system on chip (SoC) size and complexity to continue.

AMBA adaptive verification IP will be available to lead partners in the third quarter and generally available in the fourth quarter. It’s written C++ and encapsulated in System Verilog for register transfer level (RTL) compatibility. It can be licensed as an add-on to ARM’s RealView SoC designer tool for high-level modeling, or can be licensed stand-alone for use within popular verification tool flows from leading EDA vendors to provide a detailed verification of system functionality and performance. Mentor Graphics is the first major EDA vendor to ensure that adaptive verification IP functions smoothly within its verification methodology.

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