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Basic analysis and evaluation of low-dropout regulators

A spectrum of silicon technologies has evolved, each with its own inherent set of properties. Strengths, shortcomings, and trade offs are apparent with each analysis. And, designers must choose the optimal approach to meet their system objectives.

An expanding array and breadth of low dropout (LDO) linear regulator architectures have evolved, and each with its own inherent set of properties. Strengths are traded off against shortcomings, and each designer should (prudently) select the optimal solution to match system objectives. These architectures are well established and reliable, but differ widely in maturity, relative performance, and cost. Reviewing and evaluating available options can be a daunting endeavor when deciding upon the most apt solution for any specific system.


PNP-based architectures, for instance, are mature, and typically low cost, as large feature-size bipolar processes are the norm. This implementation affords very low dropout, but does forfeit performance linked to gain, output current capacity, and output capacitance/ESR essential to proper stability. Presently, it is primarily used in lower-current (<1 A) LDOs, and the ratio of PNP usage diminishes as MOS processes expand in acceptance.

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