Cadence Design Systems and Mentor Graphics have agreed to standardize on an open source methodology for verifying SystemVerilog design files. The firms’ Open Verification Methodology (OVM) is based on IEEE standard 1800-2005 for SystemVerilog verification. Its goal is a tool-independent solution that delivers on the promise of SystemVerilog with established interoperability mechanisms for Verification IP, transaction-level and RTL modles, and full integration with other languages. The OVM will include a robust class library, and be available in source code format.
“Having a methodology that works on a number of widely installed simulators and verification tools provides the confidence to move to SystemVerilog,” said Robert Hum, vice president and general manager of Mentor Graphics’ Design, Verification and Test Business Unit.
The OVM will reduce the complexity of adopting SystemVerilog by embedding verification practices into its methodology and library. The OVM will shorten the time it takes to create verification environments, easily integrate verification IP and ensure code portability and reuse.