Paul Barnard, The MathWorks’ marketing director of design automation, said the Simulink design verifier augments simulation with new verification and validation technology based on formal methods that reduce the need to hand-code tests for establishing complete model coverage and verifying requirements. The design verifier allows developers of embedded systems to obtain test cases automatically to satisfy industry-standard metrics while also helping to uncover design errors earlier in the development process when they are less expensive to fix.
Engineers can generate test inputs that satisfy standard coverage objectives as well as user-defined test objectives and requirements. These test inputs can also be combined with tests defined using measured data so that simulations are testing against model coverage, requirements and real-world scenarios.
For property proving, engineers can directly capture design requirements and performance objectives as properties in their Simulink or Stateflow models. Barnard said Simulink design verifier proves mathematically whether those properties are satisfied and, if not, provides counterexamples that would violate the properties. As a result, engineers can find design flaws, unsatisfied requirements, and unreachable states or logic that would be difficult to uncover using simulation alone.