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Renesas plans new MCU CPU architecture

Renesas Technology is developing a new CISC CPU architecture that will provide significant enhancements over 16-bit M16C and H8S CPUs and 32-bit R32C and H8SX CPUs microcontrollers in code efficiency, processing performance (MIPS/MHz) and power consumption. It aims to reduce code size by 30% and CPU power dissipation by 50%.

Renesas plans to introduce CPUs based on the new architecture to address 16- and 32-bit markets with upgrade paths for each. The new products will be compatible with existing products in terms of CPU instruction sets, peripheral register sets and development tools.

Hideharu Takebe, board director and general manager of Renesas’ MCU business group, said the new products will combine the code efficiency of M16C and R32C CPUs with the high-speed data-processing capabilities of the H8S and H8SX. He said the new CPU architecture will extend the low power consumption and low noise characteristics of both family lines.

Renesas' standard development environment, the high-performance embedded workshop, will support the new CPUs as well as its existing MCUs. Renesas will continue to work with third-party companies and actively share information concerning the new architecture via the Web under Renesas' Alliance Partner Program.

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