The automotive market is driven by safety and reliability requirements. As vehicles rely more heavily on semiconductors for their functionality and safety-critical features, the concept of Zero Defects is gaining pace. This article will examine stringent quality requirements in the context of growing use of power MOSFETs. MOSFET device packaging is highlighted as a critical element in achieving the goal of Zero Defects.
Today, the scale of electronics in a typical car is staggering when compared to everyday items like mobile phones and notebook computers. Modern cars and trucks can have up to 100 networked microprocessors running 150 million lines of code with thousands of supporting active components.
Because nearly all automotive innovation requires electronic systems, semiconductors have become the fastest growing component in a modern vehicle, with cars containing more than $1,000 worth of semiconductor parts.1 Electronic systems control all safety-critical functions such as engines, transmissions, steering, braking, and electric motors. With highly autonomous driving features coming to market now, complexity will further increase along with the risk for catastrophic electronic system failures.
Automotive Sets a High Bar for Quality
Early concerns about automotive component quality impacting vehicle safety were addressed with the formation of the Automotive Electronics Council (AEC)2 Q100 and Q101 specifications. Established by OEMs Chrysler, Ford, and Delco Electronics, the AEC’s aim was to generate common standards in the automotive industry for the qualification of semiconductors.
These standards, along with those from the Society of Automotive Engineers (SAE), the Joint Electron Device Engineering Council (JEDEC), IEC/ISO, and the International Automotive Task Force (IATF), form the basis for component requirements in automotive applications. Many larger Tier 1 automotive manufacturers still have reservations about the adequacy of these standards and impose their own customer specific requirements (CSRs) on components.
AEC Q101 Standard Needs to Evolve
A feature of the AEC “Q” standards is that they’re only used for the one-time qualification testing of components in several categories (Fig. 1).
1. AEC Q standards are used for one-time qualification testing of components.
For example, testing is rigorously defined for discrete semiconductors, but this characterizes quality of samples and predicted reliability in service rather than setting defined limits for actual allowable rates of field failures. A failure rate that was acceptable in older vehicles with relatively few electronic components can be totally inadequate in a car with thousands of components.
Even with no defects identified in a qualification test, there’s no guarantee of reliability in typical environmental conditions from −40 to 250°F. Quality control and component reliability in the ongoing manufacturing process is left to the manufacturers’ internal quality system.
A typical AEC-Q101 qualification test uses 77 parts from each of three manufacturing lots. These are tested to defined hours or cycles with no failures, which represents lot Tolerance percent defective (LTPD) = 1% at 90% confidence level, or a maximum of 0.4% defective at 60% confidence level in production testing.
Such numbers would be an alarming yield in volume production and would signal an early-life product failure rate of 11 FITs (failures in 109 hours) based on the Arrhenius equation with activation energy of 0.7 eV and 55°C use versus 175°C test temperature. A chi-squared distribution and 60% confidence level are assumed. In context, if the typical 30,000 electronic components in a vehicle all had this intrinsic failure rate, the vehicle population would have a mean time between failures (MTBF) of just three months.
Semiconductor Manufacturers Drive Toward Zero Defects
Power MOSFET use in vehicles has risen steadily and is predicted to increase from an average of a little less than 80 per car in 2017 to about 140 by 2025 (Fig. 2). Future EVs will contain around 400 MOSFET devices. MOSFETs are used in powertrain, body, safety and convenience applications, such as engine/transmission control, power distribution, automatic braking systems, power liftgate and window motors. Component failure in any of these applications could result in immobilization, injury, or, in worst case, loss of life.
2. Projected power MOSFET usage in vehicles. (Source: Infineon)
Assume the lot defect rate for power MOSFETs of 1% is screened-out in test to a residual rate of 0.001%. This would be 100 times better than the LTPD that’s tested with the Q101 specification. This 10-DPM (defect per million) failure rate would mean that about 700 cars in every million could be fitted with defective parts. With an estimated 1 billion plus cars on the roads today,3 the scale of the potential problem is again clear. Although 1 DPM has been seen in general market applications as a world-class target, 0.1 DPM heading to Zero Defects is the expected figure in automotive applications.
Quality Must be Designed In
To achieve the lowest defect rate, the manufacturer must have a quality culture that encompasses the entire product development and manufacturing process, from initial concept through design, production, and manufacturing, to final test and product fulfillment. People are central to the goal, as is full management commitment and training for all staff who are internally and externally audited to measure the trend toward Zero Defects.
An excellence program that emphasizes continuous improvement backed up with meaningful metrics must be put in place. A comprehensive datasheet and specific automotive design rules drive the product design and verification, with a validation plan to ensure that the part fits customer requirements and expectations.
Infineon, a leading supplier of automotive MOSFETs, is on its way toward Zero Defects for all of its products: DPM rates for automotive-grade MOSFETs are now proven to be less than 0.1 PPM, just below 50 PPB as of mid-2019.
The trend toward Zero Defects continues with the company’s adoption of leadless packages using internal top-side copper clips. The leadless MOSFETs are designed to meet the same reliability standards as Infineon’s leaded products and still offer higher power density. sTOLL, TDSON-8 (Super S08) and TSDSON-8 (S308) devices with this technology have exhibited high leadless-package reliability and low thermal resistance, along with having a smaller footprint and higher power density than a DPAK with equivalent RDS(on).
The leadless package frame has a wide tin-plate area for good solderability and yields a best-in-class figure of merit for the ratio of chip RDS(on) to package resistance (Fig. 3). Devices were analyzed in each package of the latest technology (SFET4/SFET5).
3. Leadless copper-clip termination yields the lowest chip to package resistance ratio.
The copper-clip termination approach also has the advantage of minimum inductance for reduced voltage overshoots and excellent EMI behavior to boost robustness in real applications (Fig. 4).
4. Leadless copper-clip termination has the lowest source and drain inductance.
Another marker for quality is the ability of the MOSFET encapsulation to adhere internally under temperature stress. Infineon’ OptiMOS devices have demonstrated the ability to withstand any delamination after 260°C preconditioning and 1000 thermal cycles (Fig. 5).
5. Infineon’s MOSFETs showed no delamination after preconditioning and temperature cycling.
Process Control and Stability is Key to Quality
High-performance design features are worthless without a production process control system that maintains quality and stability in manufacturing. Advanced statistical process control methods give real-time monitoring of key process parameters such as metal thickness and its line width, as well as resist coating and its line width. Outgoing product quality screening includes intelligent Part Average Testing (iPAT) with trend analysis of the effects of “outliers”—parts that meet the upper and lower specification limits but are beyond the expected distribution of results.
Yield loss in the various manufacturing processes is analyzed using statistical bin limits (SBL) for abnormally high (and low) figures. Wafers are optically inspected with pattern recognition to identify “at risk” die around areas where clusters of defects are occurring (Good Die, Bad Neighborhood).
Should a systematic defect be identified, the industry standard 8D (8 Discipline) problem solving sequence is invoked to prevent recurrence with systematic rollout to all locations and long-term follow-up of preventive actions (Fig. 6).
6. The “8D” problem-solving process.
With the volume of cars on the road only set to increase with a rapidly growing number of electronic components built in, traditional levels of component reliability are simply not sufficient when the consequence of failure could be loss of life. Zero Defects is the goal, and semiconductor manufacturers have leveraged AEC stress test qualification with internal design and manufacturing controls and testing to achieve the target.
Is Zero Defect possible? It is, as years of history showing more than 70% of automotive production running at Zero Defect has been achieved by Infineon. Is it worth the effort and cost? For driver and passenger safety, it’s worth every cent.
Jeff Darrow is involved with Automotive MOSFET Product Marketing at Infineon Technologies.
1. “Mobility trends: what’s ahead for automotive semiconductors,” McKinsey and Company