Model Speeds Simulation of Complex Controller

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Developing a SPICE model for National Semiconductor's LM2642 presents some significant challenges. This device, a two-phase, two-output synchronous step-down controller, is complex and contains a sophisticated soft-start, as well as several control loops, multiple channels and an internal clocking scheme that forces the SPICE time step to remain in the nanosecond region.

With a traditional transient model, a startup simulation takes several hours. However, a novel approach to modeling this complex controller in SPICE provided excellent waveform fidelity while keeping simulation run times fast. In order to reduce simulation times, transient ripple was overlaid on an average model, resulting in short simulation times while retaining the fidelity of the switching waveforms.

The LM2642 consists of two current-mode controllers operating 180 degrees out of phase with a switching frequency of 300 kHz. The two switching-regulator outputs also can be paralleled to operate as a two-phase, single-output regulator. Several device features make the SPICE model a challenge in terms of complexity, and hence, simulation speed. They include variable current sense, adjustable current limit, staged or sequential soft-start, and overvoltage/undervoltage protection, many of which are duplicated for each channel. The bottom line is that the resolution needed for the clocks and edge speeds are prohibitive. A simplified block diagram of the LM2642 is shown in Fig. 1.

Speed and Accuracy

National Semiconductor's WEBENCH online simulation tool suite combines a sophisticated Web-based schematic interface with a state-of-the-art SPICE simulation back-end. Through a typical application circuit, users can assess multiple tests scenarios and configurations.

Online simulation places a lot of requirements on the SPICE modeling process. Not only must the model simulate quickly, it must be robust. The user is allowed to present a virtually unlimited set of circuit parameters and component variations to the simulator. Tests configurations include startup, steady state, line transient, load transient and frequency response. Input stimuli, output load and component values are all at the user's disposal.

The online simulation methodology is especially attractive as it allows the user to simulate practical circuits without having to purchase software, bypass the learning curve and avoid the effort of the modeling process. The interactive nature of the environment requires the simulator to return results usually in under a minute. Longer simulation times significantly inhibit the interactive process.

The SPICE modeling process follows a pattern. First, the overall structure of the IC is reduced to subcircuit modules that represent individual function blocks. In most cases, development of models based solely on manufacturer data sheet specs results in inaccurate and/or erroneous operation. Models might be correct under certain specific conditions or operating points but not for general usage over the entire operating range.[1]

While the SPICE model does not reveal proprietary structures or parameters, it is essential to consider information beyond the scope of the device's data sheet in order to model key functions such as the error amp, output driver, slope compensation and other functions.

Once the proprietary information is understood, the data must be mapped to topological structures that perform the operation efficiently and accurately. This is one of the reasons why it's critical for the engineer who is creating the model to be familiar with the circuit application, the part's operation and SPICE syntax.

Lastly, additional models are constructed for parts used in the application circuit such as FETs, diodes and passive components.

The IC under development is simulated using startup, steady-state, line transient, load transient and frequency response in a typical application-circuit arrangement. The simulation data for key parameters (output voltage ripple, inductor current, etc.) are compared via waveform overlays with data gathered from comparable tests made in the laboratory. This is how AEI Systems verifies the majority of its models, many of which can be found in the Power IC Model Library for PSpice (EMA Design Automation,[2]

Average Versus Switching

Switching models usually exhibit the nonlinear behavior of the real component and can be connected as if you were connecting them on a breadboard. All of the switching elements in the application circuit are normally included in a full-featured transient switching model. The overall circuit operation and performance, including semiconductor losses and ringing spikes due to parasitic elements, can be analyzed. Because SMPS circuits usually operate at high frequencies and have time constants on the order of milliseconds, simulation times can be long.

Average models do not contain the switching components. They contain state equations, which describe the average behavior of the system and will vary based on the topology employed.[3-6] The “state-space-averaging” technique consists of smoothing the discontinuity associated with the transitions of the switches between their on and off states. The result is a set of continuous nonlinear equations in which the state equation coefficients now depend upon the duty cycle.[7]

State-space average models are mostly used for performing frequency domain simulations but can also be used in transient simulations. They are on the order to 100 to 1000 times faster than switching transient models and have the same general response (startup, line/load transient, etc.), albeit with the switching effects absent.

Fig. 2 shows a section of the average SPICE model topology. The full average model adds various startup features, including soft-start.

The model uses behavior-modeling blocks to calculate the average responses for the ramp voltage, duty cycle, peak current and minimum current. These are calculated based on the input and output voltages, duty cycle, switching frequency and inductance.

Referring to Fig. 2 and the equations that follow, the parameter “duty” is calculated as the operating duty cycle, which is VOUT/V(RSNS1) where VOUT = VSW1, the average value of the output node. The voltage drop due to the RDS(ON) of the MOSFET is accounted for in the V(RSNS1) calculation. IPK and IMIN are the peak inductor current and the minimum inductor current, respectively:

where I(VS1) is the output current, V(RSNS1) is the voltage across the RDS(ON) of the MOSFET, 8.2 µH is the output inductance value, and 300 kHz is the frequency of operation.

The term “Ramp” refers to the voltage that is dependent on the operating duty cycle (and includes an offset, 0.25 × V(duty) + 0.5 ). This is equivalent to the sawtooth ramp used for slope compensation. IAMP is the current-sense signal used for the current-mode control and equal to V(VIN , RSNS1) × 5.2. It senses the voltage across the RDS(ON) of the MOSFET. A scaled version of this signal is added to the ramp signal for comparison with the error amplifier output. This provides the current-mode control as well as the slope compensation.

In order to obtain the correct output voltage, we must provide an accurate average output current. The converter uses peak-current-mode control, so we must determine the peak and minimum inductor currents to determine the correct average current while producing the correct peak current for the control function. The duty cycle and switching frequency are necessary to accurately model the correct high-frequency effects, such as ripple voltage. IAMP and ramp are necessary to provide the correct modulator gain, which is crucial to the closed-loop response to line and load transients.

Fig. 3 shows the simulation results of the average model in a typical dual-channel application circuit. These results convey a significant amount of the information that is interesting to the design process.

Note that the output voltage (OUT1 and OUT2 pins on the LM2642 symbol) must be passed back into the subcircuit because they are required by the various behavioral calculations.

Average and Switching

Because switching effects are of vital importance to some performance issues, it was decided that the best way to simulate this characteristic was to add the output ripple to the average waveform response. This process turned out to be significantly faster than simulating the full transient model.

Referring to Fig. 4, the transient ripple was created from the results of an average model. These are used to derive an average value of the output voltage using a copy of the output filter (L1, R17, X10, and RL1) that is stored inside the LM2642 subcircuit.

These waveforms are also used to drive a latch that drives a voltage source BSDR1, which provides the switching output signal at SW1 to the external version of the output filter. This takes the place of the output driver stage and boot diode combination.

The nonswitched output stage is part of the state-space model. This portion of the model allows the feedback loop to be closed, which provides the time-dependent operating point (duty cycle). The switched output voltage recreates the high-frequency switching effects by creating a pulse with the correct amplitude (VIN less the RDS(ON) drop of the MOSFET) and the correct duty cycle (determined from the state-space average loop). Therefore, the switched output follows the operation conditions of the state space output but includes the switching effects of the switched voltage node.

To make the model easy to use, the subcircuit pin-out list is usually made the same as the real component package. But, in order to add the switching to the average output, it is necessary to obtain some of the quantities from the output filter and feed them back into the IC. So, unlike normal transient models where the subcircuit node list matches the IC package, a compromise had to be made due to the abstract nature of the average modeling implementation.

Fig. 5 shows the portions of the real circuitry that are required externally to the LM2642 model and those that are internally emulated by the model's averaging sections.

The Table shows a sampling of the simulation runtimes for various versions of the models, option settings and test circuits. Figs. 6 and 7 show a comparison of the average model, the average and switching model, and the bench data performance.

The LM2642 model that uses the combined switching and average approach requires the FET RDS(ON), inductor value, inductor DCR, output capacitance and parasitics (ESR) output load resistance, and frequency of operation parameters to be passed into it.

For load transients, the internal load resistance/current needs to be adjusted in parallel with the external load. For example, if a voltage-controlled resistance is used for the load, the control voltage must be passed into the subcircuit.

The use of the average model provides output data that, for most key circuit waveforms, is as accurate as a full transient implementation, while simulating much faster. The addition of the switching action, driven by the duty cycle, adds sufficient fidelity to resolve steady-state operation, evaluate parasitic effects and graphically show key switching waveforms such as output ripple voltage.

For startup line and load simulations, the average model provides sufficient large-signal accuracy with clear speed benefits.


  1. Sandler, S. and Hymowitz, C.E. “SPICE Model Supports LDO Regulator Designs,” Power Electronics Technology, May 2005, pp. 26-31.

  2. Power IC Model Library for PSpice Documentation,

  3. Basso, C. “Average Simulations of Flyback Converters with SPICE3,” PCIM, December 1996.

  4. Middlebrook, R.D. and Cuk, S. “A General Unified Approach to Modeling Switching Converter Power Stages,” IEEE PESC, 1976 Record, pp. 18-34.

  5. Vorperian, V. “Nonlinear Modeling of the PWM Switch,” IEEE Transactions on Power Electronics, Vol. 4, Issue 2, April 1989.

  6. Sandler, S. SMPS Simulations with SPICE3, McGraw Hill, ISBN 0-07-913227-8.

  7. Basso, C. Switch-Mode Power Supply SPICE Cookbook, McGraw-Hill Professional; 1st Edition, March 19, 2001, ISBN: 0071375090.

Test Description Model Configuration Run Time (sec) Settings and Test Circuit Conditions Startup Average model; one channel 14.2 TMAX 0.5 µs, 5-nF SS cap Startup Average model with switching; one channel 38.6 TMAX 1 µs, 5-nF SS cap Startup Average model with switching; one channel 95.76 TMAX 0.5 µs, 5-nF SS cap Startup Average model; two channels dual 8.86 TMAX 2 µs, 5-nF SS cap Startup Average model with switching; two channels dual 171 to 305 TMAX 2 µs to 0.31µs, 5-nF SS cap (time varies with TMAX setting) Line transient Average model with switching added 239 TMAX 0.01 µs Load transient Average model with switching added 265 TMAX 0.01 µs Steady state Average model with switching added 92.3 TMAX 0.05 µs

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