Memory plays a continually more important role in digital and mixed-signal circuits, but a key for future designs is minimizing the amount of chip area occupied by high-speed memory circuitry. According to an earlier forecast by the International Technology Roadmap of Semiconductors (ITRS), memory will occupy at least 90% of a digital chip’s area by 2013.1 The performance of system-on-chip (SoC) devices will increasingly rely
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