As he surveys his audience of system architects, designers, and methodologists, former Cadence CEO Joe Costello will kick off the 43rd Design Automation Conference (July 24-28, Moscone Center, San Francisco) by asking a pointed question: Are you going in the right direction? At a time when the EDA industry continues to suffer from limited growth, who better than a voice from EDA's past to point it toward the future (Fig. 1)?
And in Costello's view, the future for the EDA industry— as well as the electronics industry at large—is in gaming systems, multimedia equipment, and entertainment. DAC's organizers agree. To emphasize the point, this year's DAC will center on what it's calling MEGa: Multimedia, Entertainment, and Games.
In his Monday keynote, Costello will examine today's macro consumer trends in a talk titled, "iPod or Iridium: Which One Are You Going To Be?" In it, he'll expound on his vision for true technology convergence, framing that vision in terms of how the EDA industry must furnish the industry at large with the tools and technologies it needs to deliver what consumers are really looking for.
Papers, panels, and DAC Pavilion sessions within DAC's MEGa track will focus on the design challenges and design technology requirements for creating advanced multimedia, entertainment, and gaming products. At the DAC Pavilion, there'll be "teardown" talks on both the iPod and the Xbox 360. Each session will look at what it takes to get chips designed into high-volume consumer applications.
Directly to the point is a Wednesday panel session titled, "Design Challenges for Next-Generation Multimedia, Game and Entertainment Platforms." This panel will bring together experts who are defining the next generation of gaming, mobile TV, digital home, display, and multimedia processing platforms to hash out pertinent questions regarding chip architectures and key design challenges.
As always, DAC attendees will be able to roam the show floor with its booths and integrated demo suites. There, they can peruse the vendors' offerings in any and all areas related to EDA. In the balance of this article, we'll look at some of them, focusing on the ones that will enable designers to target those hot consumer-electronics applications.
ESL: FROM THE TOP
Electronic system-level (ESL) tools and methodologies continue to make inroads as design complexity forces more designers to consider upward shifts in abstraction. At DAC in 2004, Mentor Graphics made a huge splash with the introduction of its Catapult C synthesis tool, which automatically generated RTL from pure, untimed ANSI C++ code.
While the original version of Catapult C was a block-level tool, Mentor will again seek to shake up the electronic system-level (ESL) landscape with the launch of Catapult SL (System Level), which takes C synthesis up to full subsystem level (see "Abstraction = Freedom," p. 52).
Mentor Graphics isn't the only vendor continuing to ply the waters of C synthesis. Forte Design Systems will unveil the latest version of its Cynthesizer product at DAC. Cynthesizer 3.1 will incorporate new features that promote design reuse and the retargeting of high-level SystemC code to ASICs, systems-on-a-chip (SoCs), and FPGAs.
The tool enables users to quickly produce multiple RTL hardware implementations from a single SystemC transaction-level model (TLM) (Fig. 2). Each candidate RTL implementation can be optimized for various design constraints, including performance, area, and power, while being retargeted for different implementation platforms.
At DAC, Forte will participate in an ESL SystemC design methodology tutorial along with Summit Design, STMicroelectronics, Philips, ESLX, and the University of Tubingen. This full-day session focusing on SystemC-based design will take place on Monday, July 24. It'll home in on transaction-level modeling and the integration of embedded software while examining real-world user experiences.
Two other SystemC-related events on Monday will include a SystemC technology symposium from 12 to 1:30 p.m. (with a free lunch!) that will offer status updates on the SystemC technology roadmap and TLMs. From 2 to 6 p.m., the 5th North American SystemC User's Group will delve into real-world SystemC design methodologies and user experiences. Topics will include the integration of SystemC into the design flow.
The RTL portion of the design flow has become a commoditized area, more or less. Most of the innovation in EDA tools and methodologies today comes in either the extreme front-end portion of the flow (i.e., ESL) or in the extreme back-end physical implementation portion.
Yet there's always room for incremental improvements in the RTL design space. At DAC, Synplicity will deliver details on its collaboration with partners on a new IP-encryption standard. The company is proposing a methodology that supports tool interoperability. Synplicity also claims to have created the underlying technology for an industry standard to emerge.
The methodology uses openly available and tested encryption methods combined with an encryption-embedding mechanism proposed by Cadence for the next revision of the IEEE 1364-2005 (Verilog) standard. The methodology permits IP vendors to choose how far encryption persists through the design flow and includes the option for encryption all the way to silicon.
Those seeking an integrated environment for system-level design entry, simulation, and debugging might take a look at Aldec's Riviera-PRO. A new version will debut at DAC sporting a unified interface that's controlled by .tcl scripts. The graphical user interface (GUI) has the same look and feel whether it's running under Windows or Linux. A built-in HTML rendering engine permits streamlined information exchange among design-team members.
The environment supports all design-source formats, including C/C++, SystemC, Verilog, SystemVerilog, and VHDL. A built-in hierarchy viewer and database enable better visualization of the design structure, whether working online or offline (Fig. 3). Additionally, an enhanced waveform viewer provides visualization of assertions and data types from all supported sources.
For another RTL debugging option, check Concept Engineering's RTLvision PRO, which features support for Verilog, SystemVerilog, and VHDL. The tool enables engineers to quickly understand, debug, and implement their RTL code. It automatically extracts and analyzes clock trees and clock domains, providing full support for mixed-language designs. It also permits incremental design compilation for very fast design updates. Free evaluation packages are offered at www.concept.de.
ARM will use DAC to present the newest member of its RealView family of development tools, which run very fast virtual prototypes for use in developing middleware and application software. The company also will exhibit the latest extension of its AMBA Design tool, which is an IP design and delivery engine that lets users select, optimize, and deliver implementation-ready RTL based on ARM's PrimeCell IP portfolio.
THE VERIFICATION FRONT
DAC is always a premier venue for introducing new verification tools and methodologies. For example, EVE will display the latest additions to its ZeBu line of hardware-assisted verification platforms.
ZeBu-UF4, an ultra-fast platform, includes four Xilinx Virtex-4 LX200 FPGAs that accommodate designs of up to 6 million ASIC logic gates. Based on a PCI card with a mother-daughter scheme, the unit features an extensive low-voltage differential swing interconnect array implemented on a 68-layer pc board.
Depending on the design structure, when performing in-circuit emulation or executing synthesizable testbenches, ZeBu-UF4 can achieve maximum speeds of 20 to 40 MHz. In co-emulation at the transaction level, it can hit 20 MHz. ZeBu-UF4 is available now, starting at $60,000.
Also new from EVE is an RTL front end that extends the ZeBu Compiler from a gate-level netlist to an RTL design description and includes FPGA-synthesis capabilities (Fig. 4). The front end maps an RTL design into an array of FPGAs, such as those in the ZeBu-UF4, and automatically handles all required tasks like RTL parsing, synthesis, and partitioning. It supports parallel and incremental synthesis and place and route. It also enables RTL debugging by preserving RTL names in the design database. The RTL front end for the ZeBu Compiler is available now for $10,000.
Also new on the hardware-assisted verification front is the Iridium Edition of ProDesign's CHIPit platform. It supports up to 2580 free user I/Os on eight different extension-board sites. With those I/Os, users can connect to standard ProDesign extension boards such as external memories, Ethernet inter-faces, PCI Express interfaces, or customer-specific extension boards.
The CHIPit Iridium Edition handles up to six Virtex-4 FPGAs with a flexible and programmable inter-connect topology. It handles designs with up to 6 million ASIC gates. The system will be available in September. Contact ProDesign directly for pricing.
Advanced debug capabilities continue to be added to Novas Software's Verdi automated debug system. At DAC, Novas will show SystemVerilog assertion and transaction debug capabilities.
Startup ArchPro Design Automation will be at DAC with its MVSIM, a multivoltage RTL simulator that lets users examine the effects of any voltage variation at RTL to verify multivoltage functionality, connectivity, and sequencing. The tool has been upgraded to support variable delays and power/energy analysis.
With these capabilities, designers gain accuracy by analyzing gate-level simulation with realistic delays. This permits the detection of any dynamic timing failures due to voltage variations. The tool is available now. Contact ArchPro directly for pricing information.
BRINGING UP THE REAR
Joe Costello's vision for the EDA industry will take true innovation in the back end of the design cycle to be realized. Much of the activity at DAC will center on design-for-manufacturability (DFM) tools as the industry continues to search for the DFM approach that will stick in the long run. Other announcements will be in physical design itself, be it in placement and routing or in design closure.
On the DFM side, silicon complexity at 65 nm and below is forcing IC designers and mask makers to look to new post-layout tools such as design-rule checkers and reticle-enhancement technology that are customized for their specific design, process, and other proprietary requirements.
To this end, SoftJin Technologies' Nirmaan is a post-layout tool development kit that enables the creation of customized post-layout tools (Fig. 5). The alternative, which is trying to force-fit standard tools into custom applications, has often proved unworkable. At DAC, SoftJin will demonstrate an enhanced version of the Nirmaan toolkit with specific post-layout applications built using the toolkit.
Startup firm Nanno Solutions will debut at DAC this year. The company's tools use a fab's actual process-variation data and transforms it into realistic data that designers can use to improve parametric yield. These tools can be used in the front end as well as the back end of the design cycle.
One of the tools, Nanno-WiN, is a statistics-based worst-case interconnect model generator for RC delays and crosstalk. Nanno Solutions claims the tool, based on Monte Carlo simulation and probability calculations, improves worst-case corners for RC delays and crosstalk by 70% or more compared to current worst-case models based on skew. The tool costs $150,000 per year.
Shape-based physical design is at the heart of Pulsic's Unity integrated design environment. The platform's key benefit is that the design resides in one consistent database, which reduces the cost of managing tool interfaces. The Unity environment includes floorplanning, placement, routing, editing, signal-integrity analysis, and timing closure.
The first of the Unity tools to see release, the UniPlan floorplanner, features automatic block placement of both soft and hard macros. The hierarchical floorplanner is specifically focused on mixed-signal designs. Future additions to the lineup will include placement, routing, and layout-editing offerings.
While at DAC, check in on startup Athena Design Systems for a demo of its first product: a concurrent, multi-constraint IC optimization system. The company says the tool can intelligently, and incrementally, perform an analysis-optimization-repair loop on the fly using actual interconnects.
The dream of bigger, faster multimedia/gaming SoCs that work in first silicon will be unrealizable without an infrastructure at the foundries. To that end, TSMC will be at DAC to talk up its 65-nm DFM Compliance Design Support Ecosystem. TSMC has come up with a manufacturing-based unified data format to channel DFM capabilities through selected EDA tools directly to designers' workstations.
The unified format aligns DFM tools such as lithography process checking (LPC), chemical/mechanical polishing (CMP) analysis, and critical-area analysis (CAA) to TSMC's manufacturing-data format. This enables designers to use the same DFM data file no matter which vendors' tools they're using. It also enables simplified use, management, and updates to DFM analyses using these tools.