Thanks to a fast, built-in synthesis engine, Atrenta's SpyGlass 3.0 predictive-analysis tool detects very complex structural problems in register transfer level (RTL) code that would otherwise only show up at gate level. Its new GUI correlates the RTL coding violations with automatically generated schematics to help designers arrive at the best way to debug their design. As a result, the Verilog or VHDL code remains reusable for future designs.
The tool uses predictive analysis to look at a design's structure. It then finds downstream problems that are undetectable by rule checkers, simulators, and formal verification techniques.
SpyGlass' synthesis engine can synthesize a 3-Mgate design in less than 30 minutes. The results of that synthesis let the tool look at the hierarchy in the design and check for issues with inferred objects like latches, flip-flops, multiplexers, and counters. The tool then flattens the hierarchical gate-level structure to discover complex problems such as combinatorial loops, decoding errors, multiclock domains, and synchronization problems that often don't show up even in simulation.
SpyGlass' GUI displays a schematic of the synthesized logic, enabling designers to cross-probe between their RTL code and the schematic. Accurate pointers are maintained from both the synthesis level and the flat level back to the source RTL. Violations are highlighted on the schematic along with the corresponding RTL code.
Also available as an addition to SpyGlass 3.0 is SpyGlass DFT. The option adds two new engines to find testability issues at RTL. Its DFT analysis includes 66 standard checks for clocks, latches, tristate buses, RAM, scan insertion, and more. It can find sequential feedback loops that can't be initialized, tristate buses with contention possibility, scan chains with mixed edges, and other complex issues.
SpyGlass itself offers engines for RTL checking (linting), local structure, and global structure. SpyGlass DFT adds engines for functional analysis and testability analysis. The former, a cycle-based simulator, can simulate test-mode conditions. The latter checks for controllability and observability as well as initialization issues for built-in self-test (BIST) compliance. Both engines produce results that are fully back-referenced to the original RTL source code so error messages and reports point directly to the source language.
SpyGlass 3.0 is available now. Prices start at $60,000/year for an entry package. It runs on Sun/Solaris 2.5 to 2.8, HP-UX 10.2, and RedHat Linux 6.2 and above. The tool supports VHDL and Verilog and includes a new rule set for Verilog 2000. SpyGlass DFT is a $25,000/year option.
Atrenta Inc., (408) 453-3333; www.atrenta.com.