Electronic Design

Realizing the Promise of Electrically-Aware Custom IC Design

As silicon technology advances, a related increase in design complexity and uncertainty demands innovations in EDA solutions. The challenge for design teams is to improve productivity while differentiating their products. Uncertainty often results in scheduling constraints that may force a degree of overdesign. The result is conservative performance that may significantly reduce the value of moving to a new node. Increasing concerns about reliability (e.g. electromigration) produces additional uncertainty in physical design and is an inherent part of today’s design flows.

Currently the schematic (electrical) and layout (physical) design processes are performed sequentially and there is little or no visibility into the electrical consequences of physical design decisions. It is only when the layout is complete that the physical design can be verified to meet the electrical intent of the designer. When verified behavior does not meet performance or reliability requirements, the design iterates between the layout and sign-off stages until such requirements are met. Design teams have reported two to six major design iterations just to meet electromigration requirements alone. The layout changes to address the problem may not be apparent and additional iterations may be required to determine what to fix and how. Even when the fix is obvious, these modifications may influence other areas of the layout, making additional work necessary to meet the design intent.

While the uncertainty and lack of visibility reduces productivity, electrically aware design represents an opportunity for EDA companies to fundamentally change the custom design flow and directly enable product differentiation.

Realizing the Full Potential

Electrically-aware design represents a paradigm shift where the electrical analysis and verification that is now done when the layout is complete moves forward in the design process. This analysis should include accurate parasitic extraction of interconnect and device parasitics, electromigration, and IR drop as well as re-simulation using layout-based parasitics.

A near-term, stop-gap approach may allow partial layout data to be exported to verification solutions for batch-enabled analysis. It would provide an advantage over the current alternative; however, it also would interrupt the user’s work, impact productivity, and may require significant re-design based on how much of the layout has been completed since the prior check.

An ideal solution would be to assess the electrical impact of every layout decision as it is incrementally made and display the results in the same GUI environments that designers commonly use. Parasitic extraction rapidly would be computed and the results used to solve current distribution and multiple current density checks (e.g. average, RMS, and peak) throughout each net as it is routed.

This approach also would allow the designer to re-run simulation at any time with the layout parasitics, check against performance-related constraints and even graphically evaluate pre- and post-layout waveforms. What-if analysis and in-design optimization could be applied across corners, removing the uncertainty that contributes to conservative overdesign. Analysis and checking results would be updated to the screen without any lag or interruptions to the tasks being performed. Parasitic and current related constraints would be easily enabled and checked within the layout environment as the design progresses.

EDA tools need to adopt similar use models as popular business intelligence applications, where volumes of data need to be mined, processed, and presented in an actionable format. As such, users would be able to view those nets and segments of nets that exceed foundry or internally determined limits and use color-coded highlights on the layout to quickly review where these violations occur. The layout engineer would be able to move seamlessly between a tabular representation in a browser and the layout to quickly review all their options for fixing potential problems. Similarly, the designer would be able to move seamlessly between simulation and the layout to verify it meets their intent.

Consider the example of a tabular view and a graphical view of an electromigration analysis (Figure 1). In this view, the designer can sort by columns, quickly search and compare data, and cross-probe between the table and the design space.

Consider yet another example of how the same EM analysis could be displayed in the layout editor (Figure 2). Here, the layout engineer can visually see the errors and use that visualization to guide edits designed that work to fix the errors.

Net-by-net analysis and selection of more effective routing solutions would be possible. Maximum current limits are checked as routes are created and pairs of nets are verified to meet some predefined parasitic tolerance. This approach would not stop at analysis but provide guidance as to how to fix such problems through wire widening and spreading. Eventually the solution would drive routing and enable correct-by-construction layout as the last net is completed.

Requirements for Electrically-Aware Design

With each new silicon node, there is still emphasis on performance and cost, but now there also is a growing need to address reliability. To meet the goals of electrically aware design, we must meet a series of challenging requirements.

The most critical requirement is that in-design analysis must occur fast enough that a layout engineer experiences no lag or latency that would degrade productivity. Also, it needs to be fast enough to complement manual, guided, or automatic routing with little effect on performance. For most in-design operations, the required bandwidth for interactive feedback may require the use of the same types of multi-threaded architectures that new routing solutions now employ.

The ability to provide in-design electrical analysis at such speeds requires significant changes to the architecture of verification tools. Simply integrating today’s signoff technologies into existing layout tools will not provide the responsiveness needed by the designer. This is because parasitic extraction tools designed to be flow-neutral are built to efficiently process a large data set from beginning to end. In-design analysis requires an incremental approach that can isolate the design data into neighborhoods surrounding each net in order to begin applying models to the geometries almost instantly. For even modest designs, the time required to just (re)organize the data for a typical flow-neutral tool will exceed the time needed to incrementally compute resistance and capacitance. In other words, incremental extraction must be finished before the flow neutral solution really gets started.

While in-design analysis is valuable, there also is a need to parse and translate the large volumes of analysis data from simulation and from parasitic extraction of the layout (e.g. coupling caps for a large net). The requirement becomes even more challenging when used to assist and drive routing decisions. This same infrastructure should allow designers to tune a given parameter such as wire width or spacing to optimize related electrical behavior. The ability to provide parasitic-aware interactive tuning requires the extracted R and C values "trend" in the right direction as one makes layout changes. An interactive environment also requires parasitic models that provide accurate, smooth, and consistent response to the designer’s continual adjustments or tuning. Parasitic extraction solutions also need to be more flexible and responsive to rapidly changing manufacturing and design environments.


It is clear that there are a number of challenges to bring electrically aware design to reality. The most fundamental is the ability to do a real-time, in-design extraction analysis as one makes physical design decisions. This will require a fundamental shift in how verification tools evolve toward software architectures and solutions that support shape and net level extraction and electrical analysis. This shift will further require the ability to process large volumes of data very quickly, acquire and check constraints, and seamlessly communicate information between simulation and layout analysis tools. Being able to translate the designer's intent to the actual physical design, in an actionable way, will be the key to a successful solution.

As process nodes shrink, layout-dependent effects and parasitics will become so acute that layout may drive circuit design in terms of meeting performance and reliability requirements. Electrically aware design will go from an interesting concept to a requirement to be competitive.

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