Wireless Systems Design

Tool Helps Designers Find Interface Parasitics

This full-chip, post-layout analysis tool factors in nanometer-level analog effects from the blurring of device and interconnect interfaces.

As nanometer design projects become more commonplace, the side effects of shrinking process geometries also will grow familiar. The emergence of significant interconnect parasitic elements is chief among these effects—especially for 90-nm designs and below. But the challenge goes beyond merely addressing a new class of parasitic elements. At nanometer-size designs, analog effects blur the interface between traditional device (transistor, resistance, capacitance, and inductance) and interconnect models. As the world of chip design moves to smaller and smaller geometries, the point at which the device model ends and the interconnect model begins is almost indistinguishable. This "grey area" greatly affects the accuracy of analysis. Yet such analysis must be performed to ensure that the design schematic is faithfully represented by the actual circuit layout.

To address this challenge, Mentor Graphics Corp. is moving forward on two fronts. By adding a new resistance and capacitance engine to Calibre xRC, the company has built upon the geometric processing power of its Calibre line of parasitic extraction tools. It also has integrated Calibre xRC with Calibre LVS, putting the device and interconnect models together in a complete package for post-layout analysis. Finally, Mentor Graphics has developed hierarchical netlisting and optimized back-annotation capabilities between Calibre xRC and Nassda's (www.nassda.com) simulation platform, known as HSIMplus (SEE FIGURE).

Calibre xRC's resistance and capacitance engines provide several new features. For example, the resistance engine provides better fracturing. Such fracturing includes precise width and resistor location for electromigration analysis. Calibre xRC also flaunts inductance extraction and improvements in both device-pin handling and gate-pin placement. Users benefit because they gain control over gate region extraction. In addition, the algorithms are hierarchical and more efficient.

Calibre xRC's new capacitance engine delivers a much tighter correlation to field solver and silicon data. As a result, it improves the overall accuracy of results. The capacitance engine also has incorporated special models for vias, contacts, and the poly-to-contact area.

These geometric shapes are quite susceptible to elusive capacitance effects. When the new resistance and capacitance engines combine with Calibre LVS (layout versus schematic), the result is a package that can measure, extract, and analyze nanometer parasitic effects. By relying on the geometric processing strength of the Calibre product line, this combined tool can handle the characteristic effects of trapezoidal shapes, erosion, diffusion, via, and interconnect capacitance that are encountered in copper manufacturing processes. The geometrically accurate analysis, which is essential for post-layout simulation, offers an additional benefit: It results in smaller netlists, which should improve performance, capacity, and process yield.

Calibre xRC can handle very large GDSII design files. It is scalable across multiple processors and network compute resources while efficiently using shared memory. When integrated with Calibre LVS, the tool suites provide a real-world representation of the entire circuit all the way down to the transistor levels and device parameters. This representation aids the downstream data analysis of signal-integrity, timing, power, and reliability design constraints.

Through their collaboration, Mentor and Nassda are allowing designers to simulate large, complex nanometer designs. Calibre xRC can extract interconnect parasitics into a hierarchical data format. This compact, hierarchical, transistor-level parasitic data can then be back-annotated and simulated with full-chip circuit simulation tools, such as Nassda's HSIM. By using hierarchical storage with circuit hierarchy and isomorphism during simulation, HSIM achieves performance improvements for very large circuits while delivering detailed SPICE-level accuracy. As it analyzes circuit behavior, HSIM takes into account the electrical and parasitic effects of nanometer-scale silicon.

Pricing for Calibre xRC starts at $148,000. It is available now. Calibre xRC runs on Solaris, HP, and Linux.

Mentor Graphics Corp.
8005 SW Boeckman Rd., Wilsonville, OR 97070; (800) 592-2210, FAX: (503) 685-7000, www.mentor.com.

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