Electronic Design

1-GHz CPUs Among The Eye-Openers Unveiled At ISSCC 2000

As philosophers continue to argue whether 2000 or 2001 actually starts the new millennium, the IEEE International Solid State Circuits Conference (Feb. 7-9) in San Francisco, Calif., will continue its tradition of unveiling the latest in circuit developments. Next month's event will divulge details on no fewer than three CPUs that operate at clock speeds of 1 GHz, ultra-low-power DSPs, and many other breakthroughs.

Making silicon run faster has always been a challenge. For years, companies have been using ISSCC to unveil ever-increasing CPU clock frequencies (Fig. 1). This year, three companies in Session MP5 will detail 64- and 32-bit processors that clock at 1 GHz. One of the gigahertz CPUs is a version of the 64-bit Alpha processor developed jointly by Alpha Processor Inc., Boxboro, Mass.; Compaq Computer Corp., Shrewsbury, Mass.; and Samsung Electronics Corp., Seoul, Korea. The other CPUs include a single-issue 64-bit PowerPC by IBM Corp., Austin, Texas, and an IA-32 32-bit processor by Intel Corp., Hillsboro, Ore.

Many industry experts projected that at speeds of 1 GHz and higher, copper interconnects would be required to reduce the on-chip propagation delays. Well, they've been proven wrong. The firms working on the Alpha processor and the IA-32 have implemented their CPUs using seven and six layers of aluminum, respectively. IBM's PowerPC CPU, though, leverages six layers of copper metallization. But unlike the Alpha and IA-32 chips, which use 0.18-µm features to achieve the performance, IBM was able to leverage a less aggressive 0.22-µ>m process. The tighter features also allow more transistors to squeeze onto a chip (Fig. 2).

The remaining MP5 presentations include three other super-fast PowerPC processors. One is a 780-MHz implementation of the AltiVec-enhanced architecture by Motorola Inc., Austin, Texas. The chip employs six layers of copper interconnect and 0.18-µm features, and it integrates a 256-kbyte second-level cache in addition to dual 32-kbyte L1 caches. Silicon-on-insulator technology, combined with copper interconnects and 0.18-µm minimum features, lets IBM's researchers in Rochester, Minn., achieve 660-MHz operation for a 64-bit PowerPC. That's a 20% boost in performance versus a 0.22-µm implementation described last year. The third PowerPC device comes from IBM's Server Develop-ment Group, Poughkeepsie, N.Y., and its main research division in Yorktown Heights, N.Y. They will detail a 760-MHz G6 S/390 CPU that leverages a technology similar to that used for the 1-GHz processor presented in the same session.

The last high-speed CPU presentation will be by Hewlett-Packard Co., Ft. Collins, Colo. It will unveil improvements in HP's previously released 64-bit PA-RISC CPU that allowed designers to raise the clock speed to 600 MHz.

A 600-MHz Trend
Pushing CPUs to 600 MHz no longer strains the technology, as papers in Session WP25 indicate. In this venue, Sun Microsystems Inc., Palo Alto, Calif., will detail the architecture and implementation of a quad-instruction issue, 600-MHz UltraSPARC III CPU. This processor employs an aggressive 0.18-µm, seven-layer metal process that packs 23 million transistors into a 370-mm2 chip.

Perhaps the biggest draw for this closing session of the conference, however, will be the presentation by Intel Corp., Santa Clara, Calif. This company will premiere its IA-64, the first 64-bit CPU that also will provide binary compatibility with the instruction set on the IA-32 CPUs. Packing over 25 million transistors, the CPU will come in a 1012-pad organic land-grid-array package to accommodate the wide I/O buses (128 bits) used to move data to and from the chip.

Additional session highlights include two papers from Hitachi Ltd., Tokyo, Japan. The first describes a 64-bit RISC CPU that targets servers that can clock at 450 MHz. Focusing on lowering the chip's standby current, designers employed a multiple-threshold-voltage CMOS structure that helps reduce leakage currents during standby, while maximizing performance during active periods. The other paper shows off a low-power CPU that can deliver 1000 MIPS/W of throughput by leveraging a speed-adaptive threshold-voltage CMOS technology.

Highly parallel systems can achieve throughputs much greater than the clock rate. To test that proposition, designers at C-Port Corp., North Andover, Maine, will show the design of a 200-MHz communications processor that contains 17 RISC cores, 32 serial data processors, a fabric port processor, 192 kbytes of data memory, and 96 kbytes of instruction memory. Since all sections of the chip are simultaneously active, though, the chip power (with a 200-MHz clock and a 2.5-V supply) hits a peak level of 24 W.

DSP chips also are leveraging on-chip parallelism. In Session MP4, a presentation by Lucent Technologies, Holmdel, N.J., will give designers the lowdown on a quad-processor chip that can deliver a total throughput of 3.2 GOPS. The StarCore engine with the four processors can deliver 1.6 billion 16-bit multiply-accumulates/s when clocked at 100 MHz.

Though it consumes relatively little power, a StarCore-based chip would require about 800 mW when memory and logic support functions are included. But that power level is still too high, even with a reduced clock rate, to operate in ultra-low-power systems such as those in biomedical electronic systems.

Micropower DSP
To that end, designers at the Massachusetts Institute of Technology, Cambridge, Mass., have developed a micropower DSP that can run on the energy generated by a micromachined vibration-to-electric energy converter. Described in Session WP22, the chip consumes just 560 nW when powered by a 1.5-V source. Ambient vibrations are converted to electrical energy by the separate MEMS transducer and conversion IC to create the voltage source.

Other groundbreaking work on digital-signal-processing approaches will be found in Session TP14, including a 50-MOPS, 1-V processor developed by a team from Xemics SA, Neuchatel, Switzerland; Phonak AG, Staffa, Switzerland; and Frontier Design, Leuven, Belgium. The chip operates at 2.5 MHz, but it consumes just 720 mW when operating from a 1.2-V supply—low enough to let the processor go into applications such as hearing aids. The low power level is a six-fold improvement over a previous DSP design.

Low-power operation also is the focus of two additional presentations in the session—one from Toshiba Corp., Tokyo, Japan, and the other from 8x8 Inc., Santa Clara, Calif. Toshiba will highlight a 240-mW MPEG-4 chip that targets videophone systems. The chip operates at 60 MHz, and it includes a 16-Mbit embedded DRAM block along with three 16-bit RISC processors. Targeting packet audio for voice-over Internet-protocol applications, 8x8's 200-MHz, 250-mW chip can implement a complete Internet telephone, from audio samples in to compressed TCP/IP packetized network data out (see "Processor Eases Inexpensive Internet-Protocol Phone Design, Electronic Design, Jan. 10, p. 37-38).

The session's remaining papers will focus on video and audio signal processing. For instance, Fujitsu Labs Ltd., in conjunction with Fujitsu LSI Technology Ltd., both in Kawasaki, Japan, will expose the architecture of a four-way, very-long-instruction-word (VLIW) multimedia processor. This embeddable processor can operate at 350 MHz and deliver a throughput of 5.6 GOPS and 1.4 GFLOPS. To achieve this performance, designers combined the VLIW architecture and single-instruction/multiple-data execution. The processor employs a three-valued predicate mechanism, along with dual-load operation and a dual fetch capability.

TV displays are the focus of a 10-GOPS-capable VLIW processor developed at Philips Research Labs in Eindhoven, the Netherlands. The chip employs multiple data-driven processors that communicate with each other to perform real-time video processing on a maximum of 10 video streams in parallel.

A pair of presentations about image processing and compression round out Session TP14. ETH, Zurich, Switzer-land, will show off a 30-frame/s real-time image processor that can handle 1024- by 1024-pixel images at 30 frames/s. The chip performs black-current correction and per-pixel white imbalance adjustments, as well as image interpolation and color-space transformation, for a single-CCD camera head. Able to perform real-time motion-picture compression of 30-frame/s full-color VGA images, a chip developed by the Electrical Engineering Department of Tohoku University, Sendai, Japan, and the New Industry Creation Hatchery Center, also at Tohoku University, eliminates redundant calculations to speed the compression process. The chip can handle 2048 vector templates (16 elements/12 bits) to achieve the real-time compression of the motion pictures.

For registration information and program details, check out www.isscc.org. Interested parties also can contact Courtesy Associates, located at [email protected], or fax a request to (301) 353-1808.

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