Digital ICs/DSP: Build Faster Yet Lower-Power Chips With Memory IP

April 12, 2004

Addressing the shortcomings of previous blocks of memory intellectual property (IP), the Advantage series of memory IP boosts speed by 40% and reduces power by 50% over most current industry offerings. Developed for use with 90-nm process rules, the memory-IP blocks handle a host of design-for-manufacturability issues, including support for the detection and correction of soft errors. The cells incorporate the company's Flex-Repair redundancy technology and other circuits that open the door to robust memory test and repair subsystem implementation. The memory blocks are fully compatible with the company's widely used integration and qualification standards. Contact the company for licensing terms.

Artisan Components Inc.www.artisan.com

About the Author

Dave Bursky

Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.