DSP Core Performs Billions Of RISC Instructions Per Second

Capable of performing 3.2 billion RISC equivalent instructions per second with minimal power consumption, the SP-5 DSP hard and soft cores are targeted to system-on-chip and ASIC manufacturers for integration into next-generation Internet, communication and multimedia devices. The DSP core features SuperSIMD architecture, which enables up to 32 billion RISC equivalent instructions per second or 600 million MAC instructions per second with only 300 mW of power consumption. SuperSIMD provides the core with a memory-to-register file feature and the load-and-store architecture commonly found in DSP technology.