Electronic Design

DSP Core's CLIW Breeds VLIW Performance

The Carmel DSP is a 16-bit fixed-point DSP core that targets advanced communication and consumer applications. Its architecture is characterized by the flexibility of its instruction set and the high performance of its execution and addressing units. The instruction set is very customizable, due to its configurable long-instruction word (CLIW). This technology is a key differentiator between Carmel and all other advanced DSPs in the industry.

Using CLIW instructions, the Carmel achieves very-long-instruction-word (VLIW) performance at the cost of single-instruction multiple data (SIMD). The strong addressing and execution units provide a high degree of parallelism with the ability to simultaneously generate four addresses and perform six operations (2 MAC + 2 ALU + 2 move operations). This architecture is a step forward in DSP design in terms of flexibility, performance, and power consumption. CLIW technology combines VLIW's high performance and flexible control with SIMD's compact code and low power.

Carmel DSP's modified Harvard architecture incorporates separate program and data spaces. The core consists of three main modules: execution, addressing, and program and control.

The execution module contains two ALUs, two MACs, a barrel shifter, and an exponent unit. These processing elements share a set of six 40-bit accumulators. The ALUs operate on 40-bit data and allow parallel operations of 16-bit data in a single ALU. The MACs perform single-cycle 16-by-16 plus 40-bit multiply-and-accumulate operations on all combinations of signed/unsigned 16-bit operands. The MAC units also can perform addition and subtraction operations, allowing the core to complete four additions or subtractions per clock cycle.

The addressing module generates addresses for all data memory operands. In a single cycle, the core's addressing unit can generate as many as four independent 16-bit memory addresses. A wide array of addressing modes is available, including direct, indirect, index by register, and index by immediate. There are several post-modification modes such as linear, bit-reversal, and modulo.

The instruction set is powerful and flexible, yet the C-like assembly syntax makes it easy to learn and program. Nearly all of the instructions can be conditionally executed with the Carmel's predication mechanism. The hardware looping mechanism enables zero-overhead software loops nested up to five levels both for single or block instructions.

The instruction set includes most of the standard instructions found on DSPs. It also features a rich set of multiplication and arithmetic instructions, including instructions for extended precision arithmetic as well as signed and unsigned multiplication. A wide array of "special function" instructions, such as C-compiler hooks, block floating-point instructions, and special min/max instructions for Viterbi algorithms, is available as well.

The CLIW provides additional flexibility and reduced code size. The configurable instruction can execute up to six standard DSP instructions in a single cycle: 2 MAC instructions + 2 ALU instructions + 2 memory access instructions, all executed in parallel.

TAGS: Digital ICs
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