Electronic Design

FPGAs Bring Custom-ASIC Economy To System Design

Designed for cost-sensitive applications, two FPGA families tackle system designs previously considered approachable only with custom silicon.

Getting more for less is the eternal struggle of the semiconductor industry, especially with digital logic. That's why designers applaud the trend of FPGAs implemented in processes with ever-smaller feature sizes. Now, costs for many low- to moderate-density FPGAs have sunk to where they're an attractive high-volume alternative to ASIC designs.

The latest low-cost offerings from Lattice Semiconductor, the EC and ECP-DSP families, are fabricated by development partner Fujitsu on a 130-nm process. The SRAM-based FPGAs contain an array of logic blocks surrounded by programmable I/O cells (PICs). Interspersed between the rows of logic blocks are rows of configurable blocks of embedded SRAM (embedded block RAM, EBR) (see the figure).

High-performance DSP functionality comes with the ECP-DSP version, thanks to a row of DSP building blocks. Up to 10 gigamultiply-accumulates/s (10 GMACs/s) are possible when all DSP support blocks are used on the largest family member. The ECP-DSP versions contain four to 10 sysDSP blocks. Each block supports four functional elements in three datapath widths—9, 18, or 36 bits. One block can implement up to eight 9-bit or four 18-bit multipliers or even one 36-bit multiplier.

Initially, the EC family will comprise seven members. The smallest, the EC1, packs 1500 lookup tables (LUTs), two 9-kbit EBR SRAM blocks, two phase-locked loops (PLLs), and 112 I/O pads. The largest, the EC40, packs 41,000 LUTs, 70 SRAM blocks, four PLLs, and up to 576 I/Os.

The ECP-DSP series features five members. The ECP6 adds 16 18-by-18 multipliers to the EC6 resources (6100 LUTs, 10 SRAM blocks, and 224 I/O pads). At the top, the ECP40 has 40 18- by 18-bit multipliers as well as all of the EC40 resources.

For efficient implementation of logic functions, two kinds of logic blocks are included: programmable functional units (PFUs) and PFUs without RAM (PFFs). The PFUs contain the building blocks for logic, arithmetic, RAM, ROM, and register functions. The PFFs only house building blocks for logic, arithmetic, and ROM functions.

Each PIC block encompasses two PIOs (peripheral I/O pairs) with their respective sysIO interfaces. All PIOs support LVTTL, LVCMOS, HSTL, and SSTL I/O, as well as differential interfaces like LVDS, BLVDS, and LVPECL. On top of that, the PIOs blend in circuitry that simplifies the implementation of high-performance DDR memory interfaces.

The EBR blocks are large, dedicated, fast memory blocks. Each EBR provides 9 kbits of SRAM that can be configured as dual-port, pseudo-dual-port, single-port, or ROM. Memory width is programmable from 1 to 36 bits. At the end of the rows with the EBR blocks are the sysCLOCK PLL blocks. These PLLs feature multiply, divide, and phase-shifting capability. They're used to manage the phase relationship of the clocks.

Prices for all of the FPGAs haven't been finalized. With 19,700 LUTs, 46 memory blocks, and 28 18-by-18 multipliers, the ECP-DSP20 costs $59 each in lots of 1000. Lattice's own development tools and the MathWorks' Simulink tool support the FPGAs.

Lattice Semiconductor Corp.
(503) 268-8000

TAGS: Digital ICs
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