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Electronic Design

IP Cores Add Data Compression To ASICs, FPGAs

The GZIP family of CebaIP Cores from CebaTech Inc. delivers comprehensive, standards-based, lossless data compression for use in storage and data-networking ASICs and FPGAs. Integrating the GZIP IP cores onto storage and data-networking ICs can greatly reduce the operational costs of storing and transmitting data by end users of these ICs. Designers can choose from a number of available configurations to meet their desired speed, compression efficiency, and area requirements.

The GZIP cores are based on CebaTech’s integrated CebaIP Platform, which provides a modular approach to offering IP cores, enabling design engineers to quickly and easily integrate each configuration into their ASICs or FPGAs. Using the CebaIP Platform’s integrated advanced direct memory access controller with the OpenBSD software driver, designers can rapidly achieve complete compression, decompression, and encryption offload solutions.

The standards-based GZIP family conforms to the popular "deflate" standard as specified in RFC1951. File formats for both ZLIB and GZIP, as specified in RFC1950 and RFC1952, are also supported. Data rates range from 2 to 8 Gbits/s, while typical compression ratios for benchmark file sets are in the range of 2.5:1 to 3.5:1.

The GZIP family also includes optional advanced encryption standard (AES) capability with select cipher modes for securing "data at rest" inside the enterprise. AES data rates range from 3 to 12 Gbits/s. Supported cipher modes include ECB, CBC, GCM, and XTS with key sizes of 128, 192, and 512 bits. XTS is the latest recommendation by the IEEE in the P1619 standard for encryption of storage devices.


GZIP-based compression and decompression is available now for customer engagements. Future configurations of the CebaIP Platform including partial TCP/IP, VLAN, link aggregation, and large send offload (LSO) will be released later this year.


Pricing for single-user licenses starts at $150,000.



TAGS: Digital ICs
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