Typically, DSP designers are unfamiliar with FPGA design tools, and FPGA designers are unfamiliar with DSP algorithms. But when Sandia National Laboratories needed to replace an analog implementation of an IF receiver module set for a synthetic-aperture-radar (SAR) system with a digital version, field programmability drew the labs to FPGAs rather than ASICs. Using the Matlab calculation and analysis tool, the Simulink graphical simulation environment, and Xilinx's Virtex-II FPGAs and implementation tools, the researchers were able to bring the DSP and FPGA teams together through a common tool: the PC.
In doing so, Sandia Labs not only saved time but also ended up with a design platform that provided very fast and accurate system-level simulation. A traditional DSP design methodology would have taken multiple iterations, but that's not the case with this approach.
Sandia's digital SAR surveillance systems process high rates of data and must meet other stringent performance and output requirements. The software for implementing the DSP subsystem needs to be inexpensive and relatively easy to use. It's also important for the DSP and FPGA designers to work closely together.
Sandia uses MathWorks and Xilinx DSP design tools, including Matlab, Simulink, the Xilinx System Generator for DSP (System Generator), and Xilinx ISE FPGA implementation tools, to program and verify the FPGA. Sandia engineers designed, simulated, implemented, and tested each DSP building block individually in the Virtex-II platform FPGA. Next, DSP engineers modeled several DSP functional blocks in Simulink. They then used the System Generator to generate VHDL code and map certain blocks to the preverified soft DSP cores provided in the Xilinx DSP core library.
An important component of the system is a highly parallel polyphase decimation FIR filter/demodulator. This fixed-point, multirate filter was easy to design using Simulink and the Filter Design Toolbox. Sandia used Matlab to analyze the filter's performance.
The Matlab and Simulink environments were employed to test the design in hardware to reduce the risk of creating difficult-to-diagnose problems at integration time. Other components of the system were modeled in a similar way.
The DSP system is currently being implemented in hardware using Xilinx ISE implementation software and two XC2V6000 (6 million-gate) Virtex-II FPGAs.