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RISC DSP Raises Performance Bar

Setting new performance standards for low-gate-count processors, the ARC 700 RISC DSP processor employs a 32-bit synthesizable architecture to achieve 400 MHz in worst-case conditions via a 0.13 µm process through a seven stage pipeline configuration. This pipeline structure supports out-of-order completion, non-blocking access, two-level hit-under-miss scheduling, and configurable dynamic branch prediction. Additionally, the architecture allegedly reduces code size by up to 40% when compared to standard 32-bit only ISA architectures. Support for the processor consists of a suite of peripheral IP development tools and software. ARC INTERNATIONAL, San Jose, CA. (408) 437-3400.


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TAGS: Digital ICs
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