Designed for use in imaging PCs, the Sea of MMACs systolic data flow image processor uses a lattice of 49 morphology, multiply and accumulate cells (MMACs). The chip provides a peak performance of 98 GOPS with an arithmetic capability of 19.6 GMACS running at 100 MHz. Composed of about eight million gates, the device is fabricated using 0.18 µm technology and is packaged in a custom BGA. Higher speeds and larger arrays with tera performance rates are anticipated within the next two years.
Company: DATACUBE INC.
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